The Design of a Stitched, High-dynamic Range CMOS Particle Sensor

The Design of a Stitched, High-dynamic Range CMOS Particle Sensor

Zhu, J.

Theuwissen, A.J.P. (mentor)
Dupont, B. (mentor)

Electrical Engineering, Mathematics and Computer Science

Electrical Engineering

Microelectronics

2014-07-31

This thesis presents the design of a stitched, high-dynamic range particle sensor in 0.18 µm technology, which has three different configurations of 4096*4096 (4K), 8192*8192 (8K) and 12288*12288 (12K) pixels. It can be operated at 65 MHz with a target of 5 e- RMS noise and 92 dB dynamic range. The architecture of the whole sensor is explained with a functional illustration of every block. The pixel is based on a 4T pinned photodiode structure, and the high dynamic range is realized with an extra MIM capacitor in the pixel. The pixel Y-axis addressing and control are accomplished by a block called pixel row driver. For the pixel readout, in readout columns, correlated double sampling is implemented which significantly reduces the reset or kTC noise. The signal in the columns will be multiplexed and sent to 8 readout lines. Those signals on 8 lines are sent to single-ended to differential converters, and finally are read out via buffers. The digital control signals, such as the address of pixel array, signals to switch between different modes, are created from a block called digital control block, which works as an interface between an FPGA and the internal circuits. The functional simulation with parasitic resistance and capacitance and the layout of every block and the whole sensor is illustrated. The noise simulation and result analysis also are given.

high dynamic range
stitched design
CMOS image sensor

http://resolver.tudelft.nl/uuid:01c33025-8fec-4dd8-98dd-53365f7710d8

Student theses

master thesis

(c) 2014 Zhu, J.