Dynamic cache configuration for the ρ-VEX platform

The ρ-VEX is a processor designed at the Computer Engineering lab at TU Delft to be reconfigurable at runtime, resulting in a processor that can combine or separate instruction lanes according to the program requirements. The current cache for the ρ-VEX processor is direct mapped and always identical to the instruction group configuration. This...

Fingerprint Verification on the VEX Processor

The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a...

?-VEX: A reconfigurable and extensible VLIW processor

Increasingly more computing power is being demanded in the domain of multimedia applications. Computer architectures based on reconfigurable hardware are becoming more popular now that classical drawbacks are diminishing. FPGA are constantly improving in terms of performance and area, and provide a technology platform that allows fast and...