A 9-bit 33MHz Hybrid SAR Single-slope ADC

In this work a 9-bit, 33MHz hybrid SAR single-slope ADC for element-level digitization in 2D ultrasound transducer arrays is presented. This hybrid architecture consists of a 5-bit SAR ADC followed by a 4-bit single-slope ADC. In the comparator design, the dynamic comparator and the continuous-time comparator for the SAR and single-slope...

A 1 GSa/s Deep Cryogenic, Reconfigurable Soft-core FPGA ADC for Quantum Computing Applications

Analog interfacing is the only way to communicate with a quantum processor, whether it is applying qubit operations or reading their quantum states. There exist other applications where analog interfacing is abundant, e.g. sensor networks, automotive, industrial control, etc. In those applications the use of FPGAs is continuously growing,...

A ratio metric analog-to-digital converter for eddy current displacement sensors

Displacement sensors are widely employed in industry for measuring position and movement of objects as well as for measuring other physical quantities like pressure, acceleration, etc., which can first be converted into movement. This thesis describes the implementation of a ratio metric analog-to-digital converter (ADC) for an eddy current...

A 10-bit 25Msps Pipeline ADC for Companding Baseband Processing in Wireless Application

A pipelined ADC core consumes 28mW with 60.3dB SNDR, 78dB SFDR and 76dB IMD3 is obtained. Combined with expander, extra 12dB DR is achieved with equal dynamic performance because companding takes place. Compared to conventional baseband interface, power dissipation is reduced by a factor of 3.3.