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Papameletis, C. (author)Three-dimensional stacked integrated circuits (3D-SICs) implemented with through silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller and more energy-efficient chips. As all microelectronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. This thesis was executed in the context...master thesis 2012
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Verbree, J. (author)Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) is an emerging technology. It provides heterogeneous integration, higher performance and bandwidth, and lower power consumption. However, 3D-SICs suffer from lower compound yield, especially those based on Wafer-to-Wafer (W2W) stacking. In addition, testability of such...master thesis 2011
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Siauw, W.G. (author)Three-Dimensional (3D) silicon integration is an emerging technology that vertically stacks multiple silicon circuit layers. It enables a single chip to be divided over multiple layers, which are stacked on top of each other. A literature study is performed for this thesis, which presents the basic manufacturing techniques for this emerging...master thesis 2010