· · · Institutional Repository

Nederland wordt omringd door dijken. De dijken beschermen de bewoners in het achterliggende land tegen overstromingen. Momenteel worden dijken eens in de paar maanden visueel geïnspecteerd, maar dit blijkt niet voldoende te zijn. Het doorbreken van dijken wordt vaak niet voorspeld. Een aantal bedrijven ziet deze tekortkoming in een goede inspectie, en maken producten om real-time grondverschuivingen waar te nemen. De daarvoor benodigde sensoren zijn middels kabels aan een netwerkcontroller verbonden. Het dijklichaam dient echter zo min mogelijk aangetast te worden, omdat het de bescherming van de dijk doet afnemen. Dientengevolge was de vraag van de opdrachtgever om een draadloos netwerk te ontwerpen voor in een dijk, dat het huidige bedrade netwerk grotendeels vervangt. Het doel van deze thesis is dan ook het onderzoeken van de mogelijkheden van draadloze communicatie voor een dijkwaarnemend sensorsysteem. Daarbij is de thesis specifiek gericht op het softwareontwerp voor deze toepassing, wat uiteindelijk moet leiden tot een prototype. Aan een draadloos netwerk zijn andere eisen verbonden dan aan een bedraad netwerk. Zo dient er rekening te worden gehouden met het feit dat de signaaldemping groter is. Daarnaast ontbreekt de mogelijkheid voor een centrale stroomvoorziening, waardoor ieder knooppunt individueel moet worden voorzien van energie. Mede daarom is energiezuinigheid een strenge eis aan het protocol. Daarnaast behoort het bereik en de uitleesfrequentie tot de belangrijkste eisen. Het is belangrijk dat de netwerkcontroller een volledige lijst heeft van alle knooppunten die zich in zijn netwerk bevinden. Vier verschillende initialisatiemethoden zijn beoordeeld op het aantal hertransmissies en de eenvoud van implementatie. Uit de beoordeling bleek dat initialisatie met back-off de beste optie was. Een geschikte netwerkconfiguratie moet worden gekozen om te kunnen voldoen aan de eisen aan het netwerk. Een aantal mogelijke configuraties zijn: een maasconfiguratie, een multipoint-to-pointconfiguratie en een GSM-configuratie. Deze drie concepten zijn getoetst op bereik en betrouwbaarheid, energieverbruik, datasnelheid en kosten. De multipoint-to-pointconfiguratie werd daarbij het beste beoordeeld. Het ontwerp van het protocol wordt op deze configuratie ingericht. Verschillende kanaaldelingstechnieken worden onderzocht om te zorgen dat meerdere knooppunten eerlijk gebruik maken van de beperkte netwerkcapaciteit. De meest geschikt bevonden techniek is Netwerk polling, een techniek waarbij de netwerkcontroller de data van alle knooppunten één voor één opvraagt. Tot slot worden een aantal foutbeheersingstechnieken beschouwd. Een bericht dat wordt verzonden in een draadloos netwerk zal namelijk regelmatig fouten bevatten. Het ontvangen van fouten wordt opgevangen door gebruik te maken van een combinatie van hertransmissies en foutcorrectiecodes. Het Stop-and-Wait protocol is geımplementeerd voor het regelen van hertransmissies en Hammingcode als foutcorrectiecode. De foutcorrectiecode Reed-Solomon als beste beoordeeld, maar door praktische redenen is gekozen om een Hammingcode te implementeren. Met het implementeren van de initialisatie met back-off, de kanaaldelingstechniek netwerk polling en de gecombineerde foutbeheersingstechniek in een multipoint-to-pointconfiguratie is de hoofdvraag van deze thesis beantwoord. Daarbij is voldaan aan de belangrijkste eisen om het energieverbruik te beperken, een bereik van 300 meter te halen en een uitleesfrequentie van de eens in de vijf minuten mogelijk te maken. Het is aanbevolen om bij verder onderzoek te kijken naar: een andere microprocessor, het aspect synchronisatie, foutenverdeling in een ontvangen bericht (om de foutcorrectiecode beter af te stemmen) en als laatst het optimaliseren van het inregelen van de datasnelheid. Uiteindelijk zal nog een uitgebreide test met software en hardware gecombineerd moeten worden verricht.

Optical flow algorithms present a way for computers to estimate motion from the real world. Applications like cloud motion, surveillance and robot eyesight are examples of this. The focus of existing research is mainly on either fast, but poor solutions, or slow but good solutions. In this thesis an approach to improve performance through reducing computational effort of the Lucas \& Kanade optical flow algorithm is presented. An architecture of this optimised complex algorithm on an FPGA is given. After an introduction into optical flow algorithms, a high-level system design optimisation process of the large complex computing blocks will be described, in which each part of the algorithm is analysed for quality, speed and computational effort. A new smoothing filter, StackBlur, will be introduced for the first time in an optical flow algorithm. All large complex blocks are integrated into a modular high-level pipelined hardware architecture, using manually generated flow graphs and the two-process design methodology, while keeping flexibilty in mind. Complex mathematical operations including a least squares filter and an eigenvalue computation are presented. Functional correctness of the design is verified through functional and post-synthesis simulation using realistic examples. The obtained results show that performance has been improved in terms of quality and computational effort, but that especially the eigenvalue computation block still needs further improvement.

Voor een home automation-systeem zijn vele draadloze implementaties beschikbaar. In deze thesis wordt onderzocht welke van de meestgebruikte implementaties van low-power draadloze protocollen het beste geschikt is voor de draadloze communicatie in een home automationsysteem. De implementaties die met elkaar worden vergeleken zijn Bluetooth, ZigBee en Z-Wave. Dit is van belang voor het bedrijf Domatic die aan de hand van deze thesis een keuze gaat maken voor een low-power draadloze implementatie. Allereerst baseren wij ons op een literatuurstudie naar de relevante eigenschappen voor een dergelijk systeem. Hieruit blijkt dat Bluetooth het snelste informatie kan overzenden, het bereik van Bluetooth en ZigBee het beste is en dat ZigBee het meest energiezuinig is. Vervolgens zijn metingen verricht om de prestaties van de implementaties in de praktijk met elkaar te kunnen vergelijken. Hieruit blijkt dat het bereik en de stabiliteit van ZigBee het beste is en dat de sneheid van Bluetooth het beste is. Het is niet mogelijk gebleken om metingen uit te voeren voor Z-Wave. Vervolgens worden de resultaten van deze metingen geïnterpreteerd en op basis van de literatuurstudie en deze interpretatie een keuze gemaakt voor welke implementatie het beste geschikt is. Bluetooth blijkt vooral goed te presteren op korte afstanden en met weinig obstakels tussen zender en ontvanger. Zodra er een betonmuur of een verdieping tussen zit, wordt het onmogelijk een verbinding op te zetten. De doorvoersnelheid van data is hoog, maar dit gaat ten koste van bereik en energieverbruik. Aangezien bij een home automation-netwerk met name stabiliteit, een groot bereik en laag energieverbruik van belang zijn, is Bluetooth hier niet goed voor geschikt. ZigBee heeft veel van de nadelen van Bluetooth niet. Het kan goed omgaan met obstakels tussen zender en ontvanger en kan makkelijk verbindingen opzetten als de zender en ontvanger zich op verschillende verdiepingen bevinden. Bovendien is het bereik makkelijk uit te breiden door het toevoegen van eenheden die data kunnen doorsturen. Het heeft een vrij lage datasnelheid, maar daarmee wint het terrein op energieverbruik en is het mogelijk om meer apparaten binnen een netwerk te ondersteunen. Z-Wave is geschikt voor een home automation-systeem, maar er zitten enkele nadelen aan. Zo is de latency groot ten opzichte van ZigBee waardoor het langer duurt om opnieuw een verbinding op te zetten. Z-Wave is standaard niet beveiligd, waardoor eventueel kwaadwillende personen makkelijk toegang kunnen krijgen tot het netwerk. Het bereik van Z-Wave is ruim voldoende voor een home automation systeem en de hoeveelheid apparaten die aangesloten kunnen worden is ook ruim voldoende. Tenslotte is Z-Wave een gesloten standaard die wordt beheerd door het bedrijf Zensys. Alleen tegen betaling is inzicht mogelijk in de standaard. Dit zorgt voor hogere kosten en maakt een product dat gebruik maakt van Z-Wave afhankelijk van de keuzes van Zensys. Omdat ZigBee op alle punten beter dan of gelijkwaardig presteert aan Z-Wave, is ZigBee de beste keuze voor een home automation-systeem. Bluetooth presteert niet goed genoeg om in aanmerking te komen voor gebruik in een dergelijk systeem. Domatic kan dus ook het beste voor ZigBee kiezen.

Inspections on transmission pipelines in the petrochemical industry are regularly conducted in order to guarantee safety of operations. Inspection devices are sent through the lines to record sensor data, this data needs to be post-processed in order to be able to make an analysis on the state of the pipeline. In this thesis, existing software implementations of post-processing algorithms are taken and implemented in VHDL code. This code is synthesizable for implementation in a field programmable gate array (FPGA). Goal is to reduce the time require for post-processing. A test environment is implemented which is able to feed data to the FPGA and receive the processed data back. This environment consists of a Linux PC, which communicates in DMA mode over the PCI-Express bus to the FPGA. The test environment is functional, it shows a performance increase of eight to fourteen times compared to the software implementation. A proposal is made for speeding this up even more, by using concurrent processing on multiple processing nodes.

In deze thesis vindt u het ondezoek naar de beste implementatie van een op afstand te benaderen grafische gebruikersinterface, die hardware kan aansturen. Om de juiste keuze te kunnen maken, moet er onderzoek gedaan worden naar de verschillende mogelijke implementaties. Dit onderzoek is gedaan op basis van een literatuurstudie. Op basis van dit onderzoek is er een afweging gemaakt aan de hand van criteria. Hieruit is gekomen dat de beste implementatie een embedded systeem is waarop embedded Linux draait. Op dit besturingsysteem worden Apache, MySQL en PHP geïnstalleerd om te zorgen voor de benadering op afstand. Vervolgens dient een in C# geschreven programma voor de communicatie met de hardware, dit programma communiceert ook met PHP. In de toekomst kan dit onderzoek gebruikt worden om een afweging te maken voor een andere grafische gebruikersinterfaces. Eisen De interface dient voor het volgende: • schakelen van eindpunten en groepen • instellen van tijdschema’s die, eventueel op basis van sensor informatie, eindpunten of groepen in of uitschakelen • het engergieverbruik per eindpunt of groep weer geven • meerdere eindpunten in een groep plaatsen Implementaties Bij het onderzoek is er gekeken naar een hardwarematige oplossing, hieruit bleek dat hardware onvoldoende scoort op de mogelijkheid om te updaten, ook is een hardware oplossing niet goed online te benaderen. Een hardwarematige oplossing scoort wel erg goed op veiligheid. Ook is gekeken naar een oplossing met C#, deze scoort onvoldoende op de mogelijkheid om het via het internet te benaderen, wel wordt er goed gescoord op de ondersteuning. Daarnaast is er gekeken naar Java. Java scoort onvoldoende op de mogelijkheid om het te embedden, wel scoort Java net als C# erg goed op de ondersteuning. Als laatste is er gekeken naar webbased oplossingen en dan expliciet naar .NET, Java Web Start en PHP. Deze scoorden allemaal erg goed op de mogelijkheid tot updaten. Echter scoorden ze slecht op de mogelijkheid om het te embedden. Combineren van implementaties Uiteindelijk is er gekeken naar de mogelijkheid om meerdere implementaties te combineren. Zodat de zwakke punten van de ene implementatie worden opgevangen door de andere. Er is gekozen om C#, die het beste scoorde, te combineren met een webbased taal. Omdat het relatief moeilijk was op .NET op een andere besturingssysteem dan windows te draaien is er gekozen voor PHP. Ook is er gekozen om het totale systeem op embedded Linux te draaien omdat dit betrouwbaar is en niet meer kost als de alternatieven. Nadat deze implementatie gekozen was, is deze implemenatie ook daadwerkelijk gebruikt om een interface te ontwerpen voor het iNow systeem. Er zijn een aantal functies geschreven die de communicatie tussen de webinterface en de in C# geschreven controller verzorgen. Dit blijkt goed te werken, al is de snelheid nog niet hoog genoeg voor dagelijks gebruik.

Most digital circuits use a clock signal to synchronize operations, the so called synchronous circuits. Although this clock signal makes the design convenient, especially since practically all commercial EDA tools assume a synchronous design, some advantages can be exploited when using asynchronous circuits; circuits without clock signal. Those advantages can include typical case performance, low power consumption, less sensitive to variability, lower EMI admittance and protection against differential power analysis attacks. Disadvantages of asynchronous circuits include the lack of EDA tools, their sensitivity to hazards and in some cases performance loss. In this thesis, an asynchronous implementation for a scheduled data flow graph is proposed. This type of circuit contains a lot of operations with different latencies. Thus, the faster operations are delayed by the clock signal in the synchronous case. Performance benefits could be gained when using asynchronous circuits instead of a clock signal. In this case, handshake signals are used to indicate the completion of an operation, instead of a clock signal. An asynchronous LWDF filter is synthesized. This implementation is analyzed and an optimized implementation is proposed. A complete design flow is created to generate an asynchronous circuit from any given data flow graph.

The present report assesses the performance of several receiver schemes that attempt to recover as best as possible data transmitted through an acoustic underwater channel modulating a low-frequency single-carrier wave at a high data-rate for this kind of medium. The shifted Known Symbol Padding block structure is considered robust against highly variable underwater channels, which cause severe syn- chronization problems due to significant Doppler spreading. The cho- sen receiver comprises a channel estimation stage which is based on variable training sequences. Three distinct methods are compared, and provide a basis for equalization filtering. The latter is performed on the received data to estimate the transmitted message, and it is performed both in the time-domain and in the frequency-domain in order to assess which approach delivers the best results. All of the above methods assume a time varying channel impulse response. The results obtained are later compared with a Decision Feedback Equal- izer in order to conclude if they are a reliable alternative to it.

Wireless communications have numerous applications in terrestrial and space environ-ments, but for one environment the number of civil wireless applications is small. This is the uderwater environment where for wireless communications acoustic waves are used instead of electromagnetic waves. The underwater acoustic channel is a very difficult medium for wireless communications and is subject to severe multipath and Doppler effects. It is possible that each multipath component may have a unique delay and Doppler shift, so called multi-scale/multi-lag channels. This is at present a limiting factor for wireless communications underwater. At the moment always a single Doppler rate is assumed which converts to a narrowband system when re-sampled. In this report a receiver is introduced which can remove the effects of multipath and Doppler where the novelty lies in the fact that it is especially designed for a multi-scale/multi-lag channel. This is done by introducing equalizers followed by channel estimation which are both designed for a multi-scale/multi-lag channel. The designed receiver shows promising results and is able to recover the original transmitted symbols according to the simulations.

Modern embedded systems are far to complex to describe their hardware and software at a low-level of abstraction. SystemC is a popular modeling language which can be used to specify systems at a higher abstraction level. The primary way to deal with complexity in SystemC is to apply modularization. The module hierarchy of a SystemC model is dynamically constructed during the execution of the elaboration phase of the model. This means that a system designer can build regular structures using loops and conditional statements. Currently, SystemC tools can not cope with SystemC models for which the module hierarchy depends on dynamic parameters. We present a novel approach to extract the dynamically generated module hierarchy and its behavior from a SystemC model. In our approach the hierarchical information of a SystemC model is retrieved by executing the elaboration phase of the model under control of a debugger. Thereafter, the behavioral information of the model is retrieved by using a C++ compiler extension. Finally, the behavioral information is linked with the hierarchical information. Our approach is completely non-intrusive. The SystemC model and the SystemC reference implementation can both be used without any modification. The only precondition is that they both are compiled to include debug information. To identify the information which must be extracted by a SystemC front-end a SystemC metamodel is defined. This metamodel, models the module hierarchy of a SystemC model at the end of the elaboration phase. Currently, no other detailed SystemC metamodel has been published. We have implemented our approach in an open-source SystemC front-end called Systemc Hierarchy and Behavior Extractor (SHaBE). SHaBE can extract all relevant hierarchical information and a well defined subset of all behavioral information from a model. The implementation is based on open-source tools and is developed using a test-first approach during which more than 250 test cases were successfully implemented. To extract the module hierarchy from the model the source code of the SystemC reference implementation has been carefully analyzed to determine the function calls which need to be monitored. Breakpoints are placed on these function calls and crucial information is extracted by using debug commands to inspect the stack, the function arguments, the members of an object, etc. The extraction of the module hierarchy of the model has a time complexity of O(n log n), where n is the number of SystemC objects used in the model. The behavior of the model is extracted by a compiler plug-in which extracts the abstract syntax tree in static single assignment form from the source code of the functions which define the behavior of the SystemC processes. The output of SHaBE is saved in an XML based format which describes the module hierarchy and the behavior of a SystemC Model. Presently, there is no other XML format available which can be used to describe the module hierarchy of a SystemC model as well as its behavior. This front-end facilitates the development of SystemC visualization, debugging, static verification, and synthesis tools.

Today’s production processes are more and more optimized to be competitive. The production demands are increased for speed and quality. These increased demands do not pass the roll shops in the steel industry. In the roll shop periodically the rolls from the rolling mill are checked for imperfections. The imperfections are detected by special inspection systems. Improving the inspection systems can speed up the overall process significantly in the roll shop. The request for an improved inspection system results in a new generation inspection system. This inspection system should measure more signals at the same time and process the signals faster. To achieve this result the measurements are digitalized and processed in parallel on a FPGA. Speed and quality demands are also asked from the engineers by designing and maintanance of the inspection system. In this thesis a High-Level Synthesis tool is selected to implement the mathematical model of the inspection system. The tool selection is done based on a comparison between three HLS tools, namely: CatapultC, ROCCC and Compaan. For this implementation Compaan is the most promising one. Compaan is able to split the data streams processing in concurrent systems with distributed memories. With Compaan as development tool the main part of the mathematical model is implemented in four months. This is four times faster than the preceding implementation.

Planar scaling of semiconductor ICs for achieving higher integration seems to be on the brink of saturation. As an alternative solution, three-dimensional (3D) integration follows a more than Moore strategy in which circuit layers are stacked vertically. Although, 3D integration technology has moved from Lab to Fab, a complete supply chain is yet to fall in place. Due to the lack of a fully automated 3D IC design flow, realistic performance estimation at an early stage becomes imperative to ensure an efficient end-to-end design cycle. In this paper, an approach is shown for early performance and cost estimation of a 3D stacked IC in order to allow critical technology parameters to influence system design decisions. A novel methodology is proposed which explores Through-Silicon-Via (TSV) placement topologies for a 2-tier vertical interconnect across two performance corners of the TSV technology. It estimates electrical performance and TSV area penalty which are then translated to system design metrics. The methodology is applicable to digital ICs and offers flexibility in selection of the CMOS technology node and the 3D stacking granularity. Its implementation in SystemC efficiently achieves parameterizability and enables its integration into a high-level system simulation framework. By applying the methodology to a case of a 7-port 3D router it was found that, the most preferred TSV placement topology in terms of performance and cost is Isolated for 45 nm technology node and Shielded for 32 nm technology node.

Transactional memory is a lock-free parallel programming model, which aims at replacing conventional lock-based threaded programming techniques, currently used by multi-core systems. These techniques are difficult to implement and impose unnecessary overheads caused by conservative programming practices. In this thesis, the scalability potential of a transactional memory system, called TMFab, was explored for different numbers of processors and it was concluded that for more than 4 processors the system presents reduced scalability, due to an increase in the validation overhead. In response to this observation, a novel validation scheme was proposed which reduces this overhead, first by allowing multiple transactions to perform their validations and commit operations concurrently, and second by removing the need for broadcasting messages between the active transactions. A distributed shared memory scheme was used to increase the validation and memory access throughput, as well as allow for transactions to commit concurrently on different memory partitions. The two architectures were compared by means of SystemC simulation, and a maximum of 2.5x validation speedup was observed for the modified design, together with a 2.7x reduction in memory access latency. In total, the modified design achieved a maximum execution speedup of 30% over the original, for the benchmarks that were used. Furthermore, the modified system guarantees sequential consistency even in corner case scenarios.

As reconfigurable hardware such as FPGA’s become bigger and bigger, large and complex systems can be implemented in such devices. It becomes a challenge for engineers to manually convert an algorithm in an HDL, considering the pushing time-to-market constraints. High Level Synthesis tools are developed to make this process less laborious. HLS tools use the original source code and transforms this to a hardware description. The quality of the original source code is of great influence for the resulting hardware. In many data intensive applications, memory accesses form a bottleneck. To improve the performance of the hardware implementation, the execution behavoir of these accesses must first be optimized in the software source code. While doing this, an analyzer providing crucial information about the algorithm itself helps reduce engineering time. This thesis work presents a framework which is capable of providing information about memory accesses and operations executed within an algorithm. The reports containing this information can be generated on a per function or per loop basis. This enables the engineer to find loop specific information, which can be used to optimize the algorithm and to provide crucial pipeline information to the HLS tool. An Optical Flow algorithm is used as case study to demonstrate the functionality of the framework. A massive speedup of a factor of 13.7 was achieved while the area increased only with a factor of 1.47. This demonstrates the effectiveness of the presented framework.

Cryptographic devices are vulnerable to so-called Side Channel Attacks. As attackers become smarter, hardware designers and chip manufacturers need to keep up with the security demands against these Side Channel Attacks. Side Channel Attacks such as timing analysis, power consumption analysis or electromagnetic analysis, are based upon the principle that the attacker observes the behavior of the side channel (power, electromagnetic emission etc.) while a cryptographic device is performing its operations. The side channel reveals the attacker valuable information about the secret key which ultimately enables the attacker to derive the secret key. There are several counter measures that minimize the side channel information. This thesis analyzes the influence of using asynchronous logic as a practical countermeasure against Power Analysis attacks by implementing the AES Rijndael cryptographic algorithm in a FPGA device. A Power Analysis attack is a form of a Side Channel Attack where the attacker observes the behavior of the the power consumption during a cryptographic operation. A feasible asynchronous logic design style is chosen and implemented in a FPGA. In order to compare its effectiveness, a synchronous (clocked) hardware design is made in the same design structure of the AES algorithm. Power Analysis attacks are performed on both designs, and the results are compared.

This thesis presents the design and implementation of a Chip-Multiprocessor (CMP) targeted at streaming applications(e.g. MPEG, MP3). Streaming applications are applications which can be split into several distinct stages working on data elements in a pipelined fashion. We propose a distributed-memory array (MEP-MAS), where the cores communicate via message-passing, optimizing the throughput. Application tasks are dynamically scheduled by a hardware scheduler taking the consumer-producer locality into account, thereby minimizing the communication overhead. The array is evaluated in terms of performance, scalability and predictability as a function of varied input stream sizes, multiple pipelines, number of pipeline stages and traffic volume. The array is configured as a 4 by 5 mesh and has reached speedups as high as 3.6x for a 4-stage pipeline and 13.4x for a 16-stage pipeline. Our experiments have highlighted the need for a balanced workload in order to optimize the performance. Furthermore, it is shown that MEP-MAS is scalable as the speedup and throughput almost linearly increases with the the number of added pipelines. The speedup has increased from 3.6x to 13.5x and the throughput from 17k data elements per second to 65k data elements per second. Increasing the traffic volume in the network marginally affects the speedup (-1.9%). Finally, increasing the traffic volume can cause a high deviation in arrival times between two subsequent data blocks in the pipeline of up to 8%.

In this work a new location fingerprinting-based localization algorithm is proposed for an underwater medium by utilizing ultra-wideband (UWB) signals. In many conventional underwater systems, localization is accomplished by utilizing acoustic waves. On the other hand, electromagnetic waves haven't been employed for underwater localization due to the high attenuation of the signal in water. However, it is possible to use UWB signals for short-range underwater localization. In this work, the feasibility of performing localization for an underwater medium is illustrated by utilizing a location-based fingerprinting approach. Existing algorithms for an indoor environment are evaluated in this project for an underwater medium. These algorithms are based on a neural networks or maximum likelihood estimator. Further, we also consider a classical k-nearest neighbors (KNN) approach. In addition, by employing the concept of compressive sampling, we propose a sparsity-based localization approach for which we define a system model exploiting the spatial sparsity. Moreover, a recently proposed grid mismatching algorithm is also adapted to the current localization framework and its performance is evaluated. Finally, the performance of the proposed methods is compared with the existing fingerprinting-based localization approaches.

In recent years, exciting new low-power design methods have been introduced, such as: multiple supply voltages, body bias techniques and power shut-off. In order to use these low power design methods, strict requirements for both libraries and tools are needed. An additional challenge is the introduction of more accurate characterization models for newer technologies (current source models like ECSM and CCS). This has made the task of library checking a serious issue that needs to be automated. The main part of this thesis presents a checker tool that is used to verify the consistency of the different library formats (views) in standard cell libraries. The layout consistency checker in our tool checks the consistency of the layout of pins between GDSII and LEF library views; we devised a new algorithm,Grid Formation and Centre Inclusion, for this checker. The tool also verifies the pin consistency and availability of cells across other library formats, such as: Verilog and Liberty. The tool was tested using different technology libraries (such as 90nm and 40nm), provided by different vendors (such as GLOBALFOUNDRIES); multiple interfacing errors were caught using our library checker tool. A second part at the end of the thesis shows experiments with some of the low-power design techniques used during the design of a digital block, using -for implementation- standard cells from one of the libraries that have been checked with the library checker tool. Benefits of using these techniques are evaluated and trade-offs are discussed. Power-Shut Off (PSO) design technique proved to be the most effective in reducing power consumption, with power savings that reached 20%.

One of the major drawbacks towards the realization of MIMO and multi-sensor wireless communication systems is that multiple antennas at the receiver each have their own separate radio frequency (RF) front ends and analog to digital converter (ADC) units, leading to increased circuit size and power consumption. Improvements in RF and ADC technology happen at a much slower pace when compared to digital circuits, so that this problem is likely to be more critical in future. In a dense multi-user wireless communication setup, these multiple RF front ends and ADCs spend most of their power in processing signals from interfering users. The purpose of this research is to look at alternative mobile receiver architectures, from the joint perspective of a digital signal processing engineer as well as that of an RF designer. We start by specifying the need for a communion of RF and DSP techniques. We propose that advanced signal processing algorithms can be used in combination with existing circuit configurations, such as integrated phased arrays and multi-channel feedback ADCs, to perform analog interference cancellation. Interference cancellation allows for a reduced number of receiver chains and low resolution ADCs, hence reduced circuit size and power consumption. In summary, the research addresses the following questions: - Can we potentially reduce the cost and power dissipation of MIMO transceivers, by optimization across the RF-baseband borderline? - Can we design a flexible baseband platform that is tailored to low power circuits, demonstrating a potential for low cost in a dense multi-user setup? One approach to cancel interference in RF and to reduce the number of receiver chains in antenna array systems is to design RF phase shift combiners. An alternative is to integrate existing ADCs with a feedback beamformer (this setup is especially compatible with Sigma-Delta ADCs) to identify and cancel the interferer. Interference cancellation in the RF and in the mixed signal components of the receiver allows ADC units to represent the desired user more effectively for a fixed precision. For both the above mentioned architectures, we consider the hardware limitations and propose closed form solutions minimizing the overall mean squared distortion between the transmitted signals and its received estimate, and illustrate significant power savings in the receiver. In both the cases we also specify approximate solutions, when the closed form solutions are not feasible. Given such architectures, we propose techniques to estimate the changes in state of the wireless channel. Finally, we also specify that these approaches have the capacity to cancel the intermodulation products arising from the non-linearity of the RF components. On a higher level, it is imperative for the DSP engineer to abandon looking at ADCs and RF components as "black boxes" within a sensing/ communications system. For example, viewing a digitally assisted Sigma-Delta ADC as an equalizer or viewing multi-antenna RF circuits as integrated phased arrays to cancel interference may result in highly efficient joint solutions for mapping radio waves into the digital domain. Clearly, such hybrid architectures will result in DSP techniques driving the wireless revolution rather than being an afterthought for coping with the imperfections.