· · · Institutional Repository

This thesis presents a feasibility analysis for hardware acceleration of the pattern recognition algorithms used by the Media Knowledge Engineering department at the Delft University of Technology. The feasibility analysis is conducted on a number of different algorithm classes. The Parzen Window algorithm appeared to be the most suitable option for acceleration when recongurable hardware is considered. The reason for this is that the Parzen Window consists of independent calculations that can be computed in parallel. It can be computed by execution of Custom Configured Hardware Units (CCU) in Field Programmable Gate Arrays (FPGAs). The feasibility analysis presented, gave insight in the question whether it is useful to implement these kind of algorithms in hardware. Our results showed that algorithms that have independent calculations and thus are able to be executed in parallel are strong candidates for hardware implementation, certainly when the design can be executed with integer calculations. Integer calculations reduce the complexity of hardware implementation, require smaller area on the FPGA, reduce the bandwidth of the calculations and can be computed faster than their floating point version. In the future our methodology can be reused for other algorithms that have a parallel structure.

As the area of applications for Field Programmable Gate Arrays, or FPGAs, continues to expand, designers are searching for new methods to enhance the flexibility and efficiency of these devices. A technique called Dynamic Partial Reconfiguration is based on a principle of reconfiguring a small region of the FPGA, while the remainder of the device remains operational. This thesis will investigate the current status of the field of dynamic partial reconfiguration and select the most promising technique for implementation. A proof-of-concept system will be designed and implemented using the selected technique in order to clearly uncover the properties and possibilities of dynamic partial reconfiguration. The implemented system is an audio processor, capable of manipulating sound through the use of several filters. All filters can be replaced while the system remains functional by performing partial reconfiguration. As such, this system also provides a platform upon which new filters can be designed and tested. The MOLEN polymorphic processor is a processor architecture that supports the notion of partial reconfiguration. The technique for partial reconfiguration selected in this thesis will be tested for compatibility with the existing implementation of the MOLEN processor.

Dit rapport beschrijft een onderzoek naar het monitoren van bandenconditie. Dit wordt gedaan door het meten van tenminste de grootheden bandendruk en bandentemperatuur. Daarnaast is kennis over de resterende levensduur van de band gewenst. Hiervoor is de rubberdikte als maatstaf genomen. De rubberdikte vormt de basis van een model dat op basis van een aantal parameters een voorspelling doet over de resterende levensduur. Het onderzoek bestaat inhoudelijk uit vier delen. De eerste drie delen beschrijven respectievelijk de systemen voor het meten van de drie grootheden rubberdikte, temperatuur en luchtdruk. Het vierde deel beschrijft het model dat met de gegevens van de systemen een voorspelling kan doen. Alle delen hanteren dezelfde werkwijze. Allereerst wordt literatuuronderzoek gedaan, waarna als tweede voor druk en temperatuur een combinatie van bestaande meetmethoden de sensor kunnen vormen. Voor rubberdikte wordt gekeken naar een nieuwe meetmethode. Het model omvat een programma dat de meetwaarden weergeeft.

Cardiotoxicity is a common side-effect of drugs and a major cause of late-stage drug rejections, costing the pharmaceutical companies massive amounts of money. A drug is cardiotoxic when it has a negative influence on the heart. Often, it changes the electrophysiological characteristics of the heart, resulting in arrhythmia. This can have potentially fatal consequences. Thus, it would be desirable to have a reliable, early-stage indicator of the cardiotoxicity of a drug. A stretchable microelectrode array probing the electrophysiology of cardiomyocytes under influence of a drug could be a big improvement in cardiotoxicity drug screening. It has two advantages over current systems employing human embryonic stem cell (HESC)-derived cardiomyocytes. It allows anisotropic contraction of the heart cells, mimicking a real heart more closely, and it could train the cardiomyocytes; both primarily due to the stretchable nature of the device. A prototype of a stretchable MEA was designed, using the silicone elastomer PDMS as stretchable substrate and wavy gold tracks as stretchable conductors. The device consists of the following basic parts: - Support - Patterned release layer - Stretchable substrate - Electrodes - Interconnect - Patterned insulation layer - Container for nutritious solution - Cell pattern A process flow was developed to fabricate the device. The device could almost be fully fabricated. The only problem that was not solved was the failure to contact the bond pads. There was no time left to test and characterize the device.

Huidige methoden voor het observeren van de conditie van dijken zijn niet altijd even efficiënt en nauwkeurig. Het bedrijf ‘Alert Solutions’ biedt een vernieuwde, meer betrouwbaardere en efficiëntere methode aan om de conditie van dijken te meten. Het is nu nog noodzakelijk om hiervoor een kabel in de dijk te graven. Graafwerkzaamheden in dijken zijn echter aan strenge regels gebonden. Het is dus wenselijk om deze kabel te vervangen door een draadloos communicatiesysteem. De sensoren worden verticaal aan een kabel ingegraven in een dijk en blijven enkele jaren in de dijk aanwezig. De meetdata van de sensoren worden verstuurd naar een knooppunt vlak onder het grondoppervlak. Het knooppunt zal de meetdata naar de netwerkcontroller versturen, die het weer doorstuurt naar de organisatie die de dijk onderhoudt. Er is bekeken of de draadloze communicatie met huidige technologieën kan worden gerealiseerd. Het blijkt dat er geen bestaande oplossing bestaat. Daarom zullen enkele opties worden geëvalueerd om de gewenste functionaliteit te realiseren. De eerste optie is de knooppunten onder het grondoppervlak geplaatst en de netwerkcontroller bovengronds geplaatst. Binnenin deze optie zal worden gekeken naar twee mogelijke technieken die gebruikt kunnen worden, de ISM band en het GSM netwerk. De vereiste afstand die moet worden overbrugd is ongeveer 300 meter. De tweede mogelijkheid is om laagfrequent ondergronds te gaan zenden zonder enige bovengrondse structuren. De afstand die dan overbrugd zou moeten kunnen worden is 100 meter. De te verwachten verliezen van beide methodes zijn vervolgens in kaart gebracht evenals de nadelen en voordelen van beide opties. Uit de analyse van beide opties blijkt dat de eerste optie, met gebruik van de ISM -banden, de beste resultaten oplevert. Deze optie heeft beduidend minder verliezen en geeft een veel betere mogelijkheid tot standaardisering van het ontwerp. Het gebruik van het GSM-netwerk blijkt financieel onhaalbaar te zijn. De eerste optie wordt verder uitgewerkt en de keuze voor de componenten wordt gemaakt. Met deze componenten ontstaat een hardwarematige realisatie. Met dit ontwerp zijn enkele veldtesten ondernomen om te kijken of de eisen worden behaald. Uit de resultaten van de veldtesten kan de volgende conclusie worden getrokken: De meetdata uit de sensoren kan via draadloze communicatie verzonden worden. Een aanbeveling voor toekomstig gebruik is om eventueel bij dit systeem gerichte antennes te gebruiken.

VHDL and SystemC are both languages to describe or model circuits and systems. Reasons could exist for wanting to translate a model in VHDL to an equivalent model in SystemC. A system in SystemC can be needed for modeling a system with a software part, for a faster simulation, or because some tools only support SystemC. This thesis presents a tool that performs this translation from VHDL to SystemC. The tool is constructed like a regular compiler: It consists of a front-end that reads and analyzes VHDL code and a back-end that generates SystemC code. The front-end came from the FreeHDL project and we have made the back-end ourselves. The back-end generates SystemC code by traversing the tree that comes from the front-end. We have validated that the tool is suitable for simulation purposes and we have verified that the tool translates VHDL without problems in most cases we have seen in the wild.

The RFID guardian is an embedded device to protect the privacy of people using their RFID (Radio Frequency IDentification) enabled products. This BSc. project is about how version 2 of the RFID Guardian hardware was designed. Besides the description about the hardware it handles some obligatory paperwork for the design flow which was used during the hardware design.

Every year many vulnerable road users get injured or die in accidents with vehicles that could have been prevented if the vehicle driver and the vulnerable road user were aware of the dangerous situation that was ahead. Besides non-technical aids like road safety education and wearing lights for more visibility, there are numerous road safety projects. Manufacturers and governments aim at the reduction of traffic accidents. Road safety is a major concern of the European Union and therefore they have started amongst others the vehicle-to-vulnerable road user cooperative communication and sensing technologies to improve transport safety [Watch- Over] and cooperative vehicle-infrastructure systems [CVIS] projects. These projects should come up with innovative ideas to reduce the number of accidents and casualties. The innovative concept of Watch-Over is a system based on the cooperation between the vulnerable road users and vehicle drivers. By means of a wearable device for the vulnerable road user and an on-board unit for the vehicle. This thesis work contributes to this project by improving the wearable device capabilities, by increasing the working range and by adding functionality. It also contributes to the CVIS project by the integration of this cooperative approach in the their open service environment, which enables a wider use of this concept.

Wireless sensor networks are becoming increasingly popular due to their low cost and wide applicability to support a large number of diverse application areas. Localization of sensor nodes is a fundamental requirement that makes the sensor data meaningful. Energy and cost constraints only allow to equip a few nodes with a GPS device and to localize the remaining nodes with the help of these known locations and a pair-wise range measurements. Multidimensional scaling is an attractive localization technique due to a closed-form solution. It however requires pairwise measurements between all nodes to obtain the unknown node coordinates. In this thesis we investigate the feasibility of an analytical solution when some of the dissimilarity measurements are missing. We propose a least squares method to obtain unknown node positions by projecting the squared distance matrix onto the noise subspace of the weight matrix. We evaluate the proposed method for fully connected, and partially connected networks. We show that the proposed method determines the absolute node locations for a fully connected sensor network. For partially connected networks, though it is infeasible to obtain the global node locations using our method, yet we present scenarios where relative node locations can be obtained. }

Frequency up-conversion is an integral part of the (sub)mm wave integrated radar system that is currently developed at the TUDelft in the context of the MEMPIS program. The proposed up-converter IC allows the necessary signal modulation for the radar to be generated at a relative low frequency, after up-conversion to W-band takes place. In our case, the FMCW (frequency modulated continuous wave) principle is used for the actual radar operation. This up-conversion, based on analogue signal multiplication, reduces the source signal bandwidth requirement by the amount of its multiplication factor. The purpose of this work is to explore the possibility of implementing a wideband high-order frequency up-converter which suits the needs of our radar system namely, like high conversion gain, spur suppression, improved noise performance, as well as limited DC power consumption. In our system, the up-converter converts an input signal from X and Ku-band (around 10GHz) to W-band (around 94GHz). The up-converted signal is used to drive both the transmitter antenna and the receiver mixer LO port. The whole circuit includes a multiply by 8 chain and necessary gain blocks on W-band. Study of the frequency multiplication process has resulted in a carefully planned frequency allocation, as well as, power leveling for each sub-circuit. A wideband frequency doubler capable of high conversion gain and low unwanted spur generation is designed. In the multiply by 8 chain, optimum operation of the frequency doubler, as well as, on chip filtering are performed to guarantee the spectrum purity of the output signal over wide bandwidth. Two W-band medium power amplifiers are optimized for flat gain frequency response. The multiply by 8 chain provides an output signal from 80GHz to 112GHz, with an in-band conversion gain ranging from 13.2 dB to 16.6dB. The suppression of unwanted spurs is better than -40dB. The antenna driver amplifier delivers more than 3dBm output power with 3dB in-band gain variation. The LO driver amplifier delivers more than 150mV peak voltage swing at mixer LO port with less than 2dB in-band gain variation.

In this thesis , a simulation model of a MEMS gyroscope is presented. The model enables mode matching and analysis of the dynamic behavior of a gyroscope. Furthermore, the model allows the optimization the design parameters of the gyroscope. The simulated gyroscope operates at a frequency of 52MHz with amplitudes of 10nm and quality factor of 50,000. Finally, the drive mode measurements are presented at different bias voltages.

A pipelined ADC core consumes 28mW with 60.3dB SNDR, 78dB SFDR and 76dB IMD3 is obtained. Combined with expander, extra 12dB DR is achieved with equal dynamic performance because companding takes place. Compared to conventional baseband interface, power dissipation is reduced by a factor of 3.3.

Modern system-on-chip IC designs show great requirement on minimizing power consumptions. One of the low power techniques is using dynamic voltage frequency scaling for each power domain. Yet the clock generator unit is the bottleneck to apply this technique. In this thesis, we focus on the local clock generator unit solution and design three new local clock generators which share the power supply with digital blocks. The best candidate provides good jitter performance (10ps) under large power supply noise, low power consumption (900μW) and small area (90×60μm2). The influence of power supply noise on jitter of each circuit components, like voltage control oscillator, frequency divider, phase frequency detector, charge pump, loop filter and clock buffers are studied in thoroughly.

Philips Applied Technologies has developed the RT-Motion USB platform as a compact distributed real-time motion control platform, but the platform can still be improved by developing a more advanced software framework. The goal of this thesis project is to design a modular software framework to complement the RT-Motion USB platform with extendability, flexibility, and configurability. The design focuses on the extendability of the platform by developing foundation building blocks to integrate software extension modules and device drivers easily. The design emphasizes the principle of simplicity to ensure the lowest possible overhead and highest reliability. The firmware is modular, which allows each module to concentrate on its own area. The implementation of the design has been tested and is proved to provide extendability, flexibility, and configurability while incurring low overhead. The improvement to the RT-Motion USB platform is expected to extend the applicability of the RT-Motion USB platform to a broader application range.

As CMOS technology progresses to the 45nm generation and below, lots of changes are developed on material, process and structure, such as, metal gates, high-k gate dielectrics, increased mobility, low-k wiring dielectrics, and multiple layers of circuitry (3D) . These new changes provide performance improvements and economic benefit, however face challenges on gate leakage, short channel effect, power dissipation and the various (parasitic) phenomena influences the accuracy and efficiency of analog and digital design. Consequently, extraction and verification of the design under deep submicron level is a big challenge. The main objective of this project is to evaluate the capabilities of the SPACE layout to circuit extractor for extraction of the 45nm technology. Firstly, technology files for the 45nm virtual technology are developed based on the FreePDK 45nm hypothetical technology from Nangate 45nm Open Cell Library. After building the technology files successfully, several suitable examples are developed for testing the technology files and demonstrating the most important SPACE features. Moreover, SPACE and Calibre verification flows are also compared in this project. Finally, the trade-off between SPACE 2D and 3D interconnect capacitance extraction is discussed.

In this thesis, a UWB pulse generator is designed to be implemented in IBM 0.13 um technology. The pulse generator has a high spectral efficiency. Using amplitude control, any mismatch, process variation or temperature variation can be compensated for to comply with the UWB FCC mask. The pulse has an approximate duration of 2ns. The current consumption is 13mA per pulse. The power consumption per pulse is 19.5 mW. The next stage can be a power amplifier or an antenna. In case of an antenna, the effect of bond pads and bond wires are taken into account. A challenging aspect of UWB systems is their interference with narrow-band systems. Narrow-band systems send very high power signals compared to the UWB signals and thus may saturate the UWB receiver and/or prevent reliable detection of the UWB pulses. A possible solution to this problem is filtering. In this thesis, a Wireless Local Area Network (WLAN) band rejection filter for UWB applications is designed using IBM 0.13 um technology. A new filter topology is used to implement the filter. This topology has the ability to actively read all the states of an LC filter without using extra inductors. Both AC and impulse responses are presented. The filter has a notch of approximately 14dB. It can operate over the military temperature range (-40 C to 125 C). The effects of mismatch and process variations on this design are acceptable.

The plasma-enhanced chemical vapour deposition (PECVD) method is widely used compared to other methods to deposit µc-Si:H because of the high potential to prepare high quality material uniformily on a large area substrate at low temperature. This method was used to grow µc-Si:H p- and i-layers. The effect of p– layer deposition parameters on the short– wavelength response of µc-Si:H solar cells is investigated. We also investigated the influence of deposition parameters on the properties of the µc-Si:H absorber layer deposited at the a-Si:H/ µc-Si:H transition. Parameters such as RF power, silane concentration, and deposition pressure were studied. The effect of these parameters on the material properties of intrinsic µc-Si:H layers and the device performance of single junction µc-Si:H solar cells is presented. The results show that p-layer deposited at 300 seconds with 0.2 sccm diborane flow has the optimum value with respect to transparent and conductive nature. It gave a high FF and Voc when applied in a single junction p-i-n type µc-Si:H solar cells with efficiency of 5.4%. Significant gain in quantum efficiency of the solar cell was observed especially in the short-wavelength region. With the optimized p-layer and at 80 W deposition power, the quantum efficiency increased to about 65% at 400 nm when compared to the obtained value of about 35% with the same optimized p-layer deposited at 60 W. The overall results show that the spectral response is highly sensitive to diborane flow at short wavelength. The result of i-layer sensitivity study reveals µc-Si:H i-layer deposited at a low power but higher pressure has high photoresponse. The structural properties of these layers shows defects which may be related to the grain boundries and material contamination due to stress. This was evident as the film oxidizes immediately it is brought out of the deposition system for FTIR analysis, leaving the substrate with little or no films.

Bus based interconnects are commonly used to connect Intellectual Properties (IPs) on System-on-Chip (SoC). However, as the number of high performance IPs with large communication requirements in a Multi Processor SoC (MPSoC) increases, the bus interconnects become a communication bottleneck. To overcome this limitation, the bus based interconnects are replaced by Networks-on-Chip (NoC) as the interconnect for IPs in an MPSoC. The ability to support multiple protocols, both legacy and newer, is essential for leveraging the advantages of the NoC. This thesis describes the protocol conversions, or shells, we design for the aethereal NoC, to provide a unified message format for the PLB, OPB and FSL protocols. Furthermore, to tolerate the latencies when accessing memory and to increase the throughput when possible, we add support for posted write and prefetch read in the shells and we design a mechanism to coalesce multiple single transactions into burst transaction when possible. To validate our design, we prototype it on a Virtex-II PRO FPGA. We use both synthetic applications as well as real life applications to benchmark and analyze the effect of factors, like computation-to-communication ratio, various link bandwidths and compiler loop unrolling on the performance of the system. The results show that reducing the link bandwidth up to a certain point does not affect the performance anymore, as the latency associated with NoC internals becomes dominant. Also the burst transaction can sustain the performance of the system up to a certain point, when the link bandwidth is reduced. The best result is obtained using a shell with posted write and prefetch read.

Neural stimulators have the potential of becoming very important devices for the treatment of a wide variety of diseases. One of the major problems with existing stimulators is the limited waveform adjustability. This precludes the use of sophisticated stimulation programs and thereby affects the efficacy of the therapy applied. Another issue is the limitted implantability of the device, resulting in long subcutaneous wires. Because of these two reasons a new type of stimulator is required. Electrodes implanted in neural tissue are modeled using a highly non linear model with a capacitive nature. It is however shown that the response of the electrode tissue interface can be modeled accurately enough using a linear capacitive model. The physical process associated with the stimulation of neural tissue essentially comprises lifting up the tissue potential above (or below) a certain threshold value. This means that stimulation essentially is the injection of a particular amount of charge into the tissue in order to lift the potential of the tissue. Furthermore the injected charge needs to be canceled precisely in order to prevent tissue damage. First a system level design of a complete stimulator system is presented. This design includes the possibility of feedback: based on the brain activity recorded by electrodes a certain stimulation pattern is applied. After the system definition the design of the output stage, responsible for injecting the stimulation pattern into the tissue, is treated. Most existing stimulators use a current based architecture in which the charge is controlled by enabling the stimulator for a certain amount of time. Voltage based stimulation however is shown to have a higher power efficiency. A novel type of voltage based architecture is proposed using indirect current feedback of the tissue current. Using a current integrator with a very high dynamic range the injected charge can be controlled very precisely, while any arbitrary voltage waveform can be used for stimulation. Circuit simulations prove the feasibility of the approach and show a charge mismatch in the order of 0.1% is possible, paving the way to full charge balancing. Furthermore, they predict correct functionality over all process corners, including mismatch. The system only uses a singleended supply and the quiescent power consumption of the system is less than 17 μW. Therefore it can be concluded that the novel approach for the output stage design proposed in this thesis allows the use of a very versatile stimulator; any arbritrary waveform can be injected while assuring charge balancing. Furthermore power consumption is minimized in order to relax the requirements for the battery and thus improve the implantability of the system.