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In the development of wireless sensor networks, the lifetime of a sensor node is always a key design consideration. Since the battery in a sensor node can usually not be recharged or changed, power management is an effective way to extend the network lifetime. The wireless transceiver, also regarded as the ‘main radio’, is a relatively power hungry component in a sensor node. Therefore, an auxiliary always-on hardware ‘wakeup radio’ was proposed in order to reduce the overall power consumption. The wakeup radio listens to the wireless channel whereas the main radio is only active for a rather short time when the wakeup radio receives the packet with a certain pattern. Consequently, the power efficiency becomes a primary concern in the design of wakeup radio. This thesis focuses on the low power design and implementation of a digital baseband subsystem in the wakeup radio. Firstly, the architecture and details of the subsystem are described. Then the design is verified by both a Spartan-3 FPGA board and TSMC90 chips. The design is functional as designed. In the end, the chip measurement setup and results are discussed. The power consumption varies from 2.1 μw to 8.4 μw, within our design target of 10 μw. To our knowledge, it is the first work on the digital implementation and chip measurement of the wakeup radio.

The Universal Transducer Interface (UTI) is a mass-produced interface circuit which can realize the functions of measuring signals of various sensors such as capacitive sensors, resistive-bridge sensors and resistive sensors. For some of the front-ends, an instrumentation amplifier, which is implemented with dynamic-element-matching (DEM) for its feedback structure, is integrated in the chip. In certain UTI modes, this amplifier is used to amplify small output signals of a resistive-bridge sensor or a single resistive sensor before it enters the applied modulator. According to customers’ complaints, the UTI doesn’t work well. This thesis describes how with systematic investigations three problems have been identified. The first one is that undesired offset is introduced by the limited common-mode rejection ability of the instrumentation amplifier. The second one is that for input common-mode voltages higher than 3.4V, the On-resistances of the applied NMOS switches that control the DEM loop, cause the system to be out of function. The third one is that the electromagnetic interference can introduces unwanted noise in the wiring of the external resistive-bridge sensor. Two dynamic-offset-canceling techniques have been proposed and one of them has been realized on board. With these techniques, the offset has been successfully reduced from up to 200μV to about 7 μV. The noise introduced by interference can be eliminated by applying proper shielding.

Millimeter wave sensor and communication technology may prove to be one of the key technologies of the 21st century covering a broad range of applications including high-speed telecommunication, medical diagnostics and security. The ultimate (commercial) success of these systems depends on their monolithic integration which brings about significant size and cost reduction. A crucial element in such systems is the antenna element which has to be able to send and receive signals in a desired direction in space with sufficient angle resolution. The traditional way to realize such a component is by placing a conventional antenna with a broad predefined radiation pattern in front of a parabolic reflector to achieve a high angle resolution (directivity). However, this approach demands the mechanical adjustment of the reflector to change the direction of transmission/reception: a solution not viable for integrated applications. In this project we aim for the design and realization of an electrically tunable reflector as an alternative. The reflector consists of a large number of small antenna elements each terminated by an electrically tunable capacitor (varactor). By tuning the bias voltage of the varactors, the reflection properties of the elements and thus of the whole reflector can be adjusted. Of particular importance here is the resulting antenna radiation pattern (directivity) and beam steering capabilities.

The aim of this thesis project is to design and fabricate a high efficiency on chip cooling device based on the Peltier effect. Bismuth telluride (Bi2Te3) and antimony telluride (Sb2Te3) are employed to form thermocouple for their high Seebeck coefficient and high figure of merit. The models of the devices are simulated in the software program COMSOL, and based on simulation results, a set of masks are designed. The patterning methods are investigated, and wet etching is chosen for its simplicity and smooth edge, although the lateral undercut is 4-5 times of the layer thickness. The wet etchant is HCl: HNO3: H2O =3:1:2 for Bi2Te3, and HNO3: H2O =1:1 for Sb2Te3. The devices are tested on the probe station and under the thermal camera. The combined Seebeck coefficient is 282μV/K. A maximum cooling temperature of 3.3K is observed.

With the so many available sorts of E-paper, the optimal performing and consumer friendly E-paper needs to be found in order to win the E-paper market. As result of this, researchers from the TU Delft are currently developing a technology that can replace all ordinary papers by one single device, which has outperforming characteristics compared to the current E-papers: Super E-paper. In order to launch this superior product, a research needs to be conducted with regards to the optimum driving method of the Super E-paper. This thesis shall not only investigate what the optimum driving method of the Super E-paper is, by applying different types of power to the product. But also describe our steps towards this measurement by sharing background knowledge, linking theory to practice, designing the source that will be used for our Super E-paper measurements. For the measurements, several variables are analysed: · Voltage amplitude · Frequency of the source · Duty cycle of the source

This thesis is about an innovative technique of designing a precision current mirror which enables us to achieve a very high DC accuracy with ripple free output signal, without using an external low pass filter to suppress the unwanted ripple. The word 'precision' here means that the current mirror has an accurately defined input-to-output relationship in terms of gain, linearity and offset. The idea behind this design is basically a combination of trimming followed by Dynamic element matching (DEM). Test chips are fabricated to test the functionality and performance of the new concept. The DC accuracy obtained from the mirror is 0.18% and AC ripple is suppressed by 50X compared to state-of-the-art. The chip area (without padring) is 0.84mm2. The supply voltage ranges from 11V to 40V. This design was done using a high performance analog process (50HPA07HV) from Texas Instruments (TI). This is a high voltage BiCMOS process (40V compatible) having minimum gate length of 0.6um analog devices compatible with 0.3um gate length digital.

Electrical analysis techniques are introduced to determined the type of the diodes, whether they are Schottky diodes or pn junction diodes.

This research work aims to gain understanding of the power amplifier (PA) operating as a linear PA under low power drive conditions and as a switch-mode PA in high power drive conditions both with the same Class-E load. Two approaches were taken here. Firstly, an analytical approach was developed to investigate the switching operation of conventional Class-E amplifier. The model used in the analytical approach takes into account the non-ideal switch resistance, finite dc-feed inductance, finite loaded quality factor, and arbitrary switch duty-cycle. This approach presents an accurate closed-form expression for modeling Class-E power amplifier. Using this approach, the frequency response of conventional Class-E power amplifier was studied in detail and the impact of the loaded quality factor and finite dc-feed inductance on the broadband performance was analyzed. It shows that the Class-E PA with conventional load network cannot provide stable output power, efficiency, and reliable operating voltage conditions across a broad frequency band (Bandwidth > 40%). In addition, study of the load impedance of the amplifier indicates that the Class-E PA is sensitive to the load phase angle at fundamental frequency. In the second approach, a purely linear voltage-control current source was constructed numerically as a way to represent the transistor. Based upon that model, the influence of non-ideal drive signal on the switching operation was studied. It shows that the power amplifier with finite dc-feed inductance is tolerant to a non-ideal drive signal. For the rise and fall times of 25%T, only 5% drop in drain efficiency was found for the optimum finite dc-feed inductance. The performance of that model in linear operation was also investigated. The results agree with the classical theory for linear power amplifiers. The linearity (intermodulation distortion and 1dB compression point) was analyzed by using a realistic transistor model (an extended drain NMOS). It shows that the Class-B biased PA with finite dc-feed inductance can provide not only similar IMD3 feature as the optimum Class-AB biased PA with RF choke does, but also high efficiency simultaneously. Based upon this device, a systematic design process was applied to implement a broadband high efficiency Class-E PA. The PCB for this broadband high efficiency Class-E PA was fabricated. Good agreement was found between the simulation and measurement. The measurements indicated that the PA achieves a drain efficiency >67% and a PAE >52% with a Pout >30dBm from 560-1050MHz, where the output power variation is within 1.0dB and efficiency variation is within 13%. The highest efficiency is observed at 700MHz from a 5.0V supply with peak drain efficiency of 77% and peak PAE of 65% at 31dBm output power and 17dB power gain. When using dynamic supply modulation, the PA achieves a PAE of 40% and a drain efficiency of 60% at 10dB power back-off across the frequency band 500MHz to 1100MHz.

With the rapid growth of wireless communication systems, there is more and more demand for radio frequency power amplifiers (RFPAs) in base stations to be power-efficient so as to reduce the cooling and electrical power cost. Besides the efficient requirement, wide-band working frequency and compact PCB size are also attractive for cutting more cost. This thesis deals with a switch-mode Class E power amplifier which provides wide-band, highly efficient and compact size performance, with a 60W GaN HEMT device. A mathematical model for Class E amplifier is presented and analyzed. Based on the model, a novel design procedure for wide-band power amplifier design is proposed. The input/output matching networks in the amplifier are built by bondwires and pre-matching capacitors so as to give an extremely compact size. The 60W compact wide-band power amplifier is then implemented with PCB to verify the concept. A wide-band measured output power performance is observed over 1.7GHz - 2.3GHz in the range of 40-65W and the measured drain efficiency is between 66% and 74%; measured PAE is between 61% and 70%. Transducer power gain is 12dB ± 1dB over the frequency range. Besides the amplifier, additional work is about large signal device modeling with PolyHarmonic Distortion model which is based on acquiring X-parameters of a device.

Most digital circuits use a clock signal to synchronize operations, the so called synchronous circuits. Although this clock signal makes the design convenient, especially since practically all commercial EDA tools assume a synchronous design, some advantages can be exploited when using asynchronous circuits; circuits without clock signal. Those advantages can include typical case performance, low power consumption, less sensitive to variability, lower EMI admittance and protection against differential power analysis attacks. Disadvantages of asynchronous circuits include the lack of EDA tools, their sensitivity to hazards and in some cases performance loss. In this thesis, an asynchronous implementation for a scheduled data flow graph is proposed. This type of circuit contains a lot of operations with different latencies. Thus, the faster operations are delayed by the clock signal in the synchronous case. Performance benefits could be gained when using asynchronous circuits instead of a clock signal. In this case, handshake signals are used to indicate the completion of an operation, instead of a clock signal. An asynchronous LWDF filter is synthesized. This implementation is analyzed and an optimized implementation is proposed. A complete design flow is created to generate an asynchronous circuit from any given data flow graph.

A voltage controlled oscillator (VCO) is an integral part of a phase lock loop (PLL) which by itself is the core of the frequency reference in a radar system. The generation of the in-phase and quadratue signals is crucial for many radar applications. A 60GHz quadrature voltage controlled oscillator (QVCO) is presented in this thesis. The design is implemented in 130nm SiGe BiCMOS technology from STMicroelectronics with an fT of 220GHz and fMax of 320GHz. Two Colpitts oscillator cores are series coupled to each other to generate the required in-phase and quadrature signals. The QVCO achieves a simulated tuning range from 53GHz to 59GHz with a tuning voltage from 0.5V to 2.3V. The phase noise is better than -76dBc/Hz at 1MHz offset from the carrier over the whole frequency tuning range. The total power consumption for the QVCO core is 28mW. The chip has been submitted for tape out in June 2010 and will be back for measurement in due time.

As the first stage of the amplifier chain aiming for the base station applications, a highly linear low noise amplifier (LNA) dictates very high performance for optimum coverage with a best signal quality. In today’s commercial market, the GaAs enhancement-mode pHEMT based LNA is dominant. However, a SiGe-based LNA, due to its high integration, is still attracting the interest from industry. In this thesis, the highly linear SiGe-based LNA design procedure is presented. For the fully-differential LNA design, the base tuning and emitter tuning, which both belong to the out-of-band matching technique used to increase linearity, are analyzed in details. Although the base tuning suffers more from mismatches in comparison with the emitter tuning, it is proved that proper choice of the harmonic trap capacitor is able to mitigate this effect, which can trigger a higher linearity. For the single-ended LNA design, the out-of-band matching is still feasible for narrow band applications. A compact topology of highly linear low noise amplifier which is composed of an emitter inductive degeneration and out-of-band matching core is proposed. Moreover, a modified neutralization function block based on on-chip transformer and bondwire inductor is also proposed. For this configuration, simultaneous noise/input matching, linearity improvement and a good reverse isolation is able to be achieved. It proved effective and convenient for a packaged monolithic RF chip. However, most input-referred linearity optimization techniques focused on the harmonic termination design at the input part, which leads to a narrower bandwidth and a higher noise figure due to extra losses in practice. To avoid these issues, an innovative linearity improvement method based on optimizing the output load is proposed. A novel two-stage highly linear LNA is designed to validate this theory. It achieved a power gain of 29dB and noise figure of 0.7dB at 1.7GHz, while only consumed 41mA from 3.3V supply. The OIP3 can be better than 38dBm from 1.2GHz to 2GHz. The input-referred 1dB compression point is -5dBm. The simulated result is the state-of-the-art among the current existing SiGe-based LNAs for base station applications. The design, as a part of a highly linear monolithic RF receiver, has been carried out using NXP QUBiC4x BiCMOS technology.

This thesis presents the design of a pixel level analog-to-digital converter (ADC) circuit for hybrid CMOS image sensors. There are several methods to increase the dynamic range of the sensor through the readout algorithm. The multiple sampling method can increase the dynamic range (DR) without a loss of signal-to-noise ratio (SNR). The idea is to acquire several images during one frame. Based on the multiple sampling method, the method described in this thesis uses the special feature of the pinned photodiode to select the charge transfer time locally to change the total integration time in one frame based on the input light intensity. The comparator is reused during the different conversion phases to save power and area. Only one comparison is needed after each charge transfer, so compared with traditional multiple sampling method for DR enhancement this method can save a lot of power. In-pixel memory is used to store the converted data, and these data are read by column wise current sense amplifiers. The simulation results show that the charge transfer of the pinned photo diode is controlled locally and for a 7-bit dynamic range enhancement the additional power is only 2.2% compared with no DR enhancement.

This thesis is based upon the business plan of R:eFlex, which is part of the Bachelor Graduation Project of TU Delft. R:eFlex is a start-company that wants to introduce electronic billboards using Epaper, which is currently under development at DIMES; the ‘Delft Institute of Microelectronics and Sub-micro-technology, affiliated to the TU Delft. In interviews conducted for the business plan with several companies expressed interest in this idea. This report describes a design of an electronic billboard system that can be easily created using super E-paper.

Currently, a low cost, single-chip multi-band WCDMA/GSM transceiver is needed for the 3G segment of the cellular communication that provides backward compatibility with the 2G GSM network. In this thesis, a novel, multi-band, low noise transconductance amplifier (LNTA) is presented. The LNTA has three stages, which are the transconductance, feedback and single ended to differential conversion stages. In order to eliminate the bulky and lossy passive balun deployed for single ended to differential conversion before the LNTA, a single transistor was used preceding the LNTA in order to provide a differential output. The LNTA is designed with a large transconductance in order to suppress noise in the second stage mixer of a wideband transceiver. Hence, CMOS transconductor was employed as the input stage, and the transconductance of the LNTA was stabilized by the constant gm biasing circuitry. Moreover, an active feedback technique was developed to increase the linearity of the LNTA. Finally, a dual band matching network was used in order to realize multi-band operation. The LNTA presented in this thesis achieves 1.8dB – 2.8dB noise figure in the WCDMA bands. S11 is below -12 dB from 870MHz to 960MHz and it is below -15dB from 1.8GHz to 2.2GHz. The worst case out of band IIP3 is -14dBm for low band and -8dBm for the WCDMA high band. The total current consumption is 9mA from a supply voltage of 1V. The LNTA has been designed in IBM’s 65nm CMOS process technology.

Testing of Analog/Mixed-Signal (AMS) integrated circuits (ICs) has been one of the most challenging topics in the test technology community; this is because it is very time consuming and it is hard to distinguish between pass and fail as it is the case for digital circuits. For some applications, such as automotive industry, the quality requirements for AMS ICs can be as severe as zero Parts Per Million (PPM) level. This requires, in addition of optimizing test time, also test for all possible defects in the IC. Bridges and opens are the common defects considered for AMS circuits; they are analyzed in Defect Oriented Testing (DOT) flow in order to develop appropriate test program. With high/severe quality requirements new failure mechanisms have to be considered for test purposes. Investigating such defects and their impact on the quality is important especially for zero PPM level application. This thesis investigates the effect of dislocation defects for an NXP AMS IC which is an automotive product, manufactured in 140 nm technology. Dislocation defects cause leakage related failures while crossing a PN-junction of the device. It is very challenging in AMS testing to detect these defects. A schematic-based extraction methodology is proposed to extract the dislocation defects based on studying the cross-sections of different devices present in an IC. Using the proposed methodology for extraction, the defect list is limited to only 8% of the total active devices present in the IC. This is useful in guiding the failure analysis process and reducing the simulation effort considerably. These defects possess a high resistive signature and were simulated for different sets of resistance values. It was found that the detectability of these defects decreases as the resistance value is increased. Test selection algorithms such as ‘greedy’ and ‘unique detects first’ are used to obtain an optimal test set which is able to detect all the defects, including dislocation defects. The performance of both the algorithms in terms of test reduction is compared. The optimal test set obtained is used for validating the production data consisting of 1.3 million dies. The escaped ICs are diagnosed using a fault dictionary approach. The diagnosis results reveal that the current production data set does not suffer from dislocation defects. However, extra tests obtained for detecting dislocation defects can be kept for advanced technology nodes in the future, if these defects show up in the production environment.

Operation at millimeter-wave frequency, where up to 7GHz of unlicensed bandwidth is available in the 60GHz band, provides an opportunity to meet the higher data rate demands of wireless users. Advancements in silicon technology permit one to consider exploiting the 60GHz band for commercial applications (e.g., short range, wireless HDTV transmission) for the benefit of end users. This could enable, for example, wireless streaming of uncompressed high-quality video packets of a movie in few seconds due to data rates as high as multi gigabits per second. In this thesis, the design of a receiver front-end circuit for operation in the 60GHz range in 90nm CMOS is described. The thesis includes design details of the blocks used in the receiver, including: quadrature voltage-controlled oscillator (QVCO), local oscillator (LO) buffers, divider chain, low-noise amplifier (LNA) and mixer. The QVCO predicts 56.8-64.8GHz tuning range from schematic simulations. The divider chain has 15GHz locking range at rail-to-rail (0.5V-peak) input signal. The LNA and mixer combination achieves a maximum conversion gain of 26.77dB and a noise figure of 5.88dB. The output -1dB compression point is +6.3dBm and IIP3 is -8.6dBm. The complete front-end consumes 91.7mW from 1V supply. Physical layout of the test circuit and post-layout simulations for the implementation of a test chip including the QVCO and the first stage divider are also presented. Post-layout simulations show a maximum phase noise of -97.4dBc/Hz over 55.4-61.7GHz tuning range.

The efficient use of the power budget in mobiles and small satellite applications is of primary importance because of the reduced size of the power sources. The limited power supply has to be spent wisely. In a transmitter, the power amplifier is the main consumer of that budget, which is why it has to be as efficient as possible. Unfortunately, high efficiency in power amplifiers is strongly related to non-linearities and hence distortion. However, several techniques help to improve the linearity of the power amplifier. One of the most powerful means to linearize a system is using negative feedback. In this work the analysis of a mixed-signal Cartesian feedback is carried out. Cartesian feedback offers two challenges: stability and phase shift. In a feedback system with a time delay in the loop, instability is likely to happen. Phase shift is the result of the time delay in the loop and non-linearities of the power amplifier. First a model of the mixed-signal system is proposed, and the stability of the system is analyzed. Second, a model of the phase shift is proposed, and the conditions under which it can be reduced are given. The model is implemented in the digital domain. In order to realise this a design consisting of a phase shift detector, a signal rotation and a magnitude computation was created in VHDL and then synthesized, while targeting FPGA and 90nm CMOS technology. An FPGA implementation shows a power consumption of 33.31[mW] for a total budget of 1.7[W] (1.96% of the total budget). The system reaches a 60° of phase margin with a loop gain of 10, for a bandwidth of 9.6[kHz]. The results show that it is possible to improve linearity at the expense of bandwidth when using Cartesian feedback.