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In this thesis, the development and implementation of a high-precision Sigma-Delta modulator is described. The objective of this thesis was to investigate the possibility of merging a current mode feedback instrumentation amplifier with the following analog-to-digital converter into one sigma-delta modulator. For this purpose, a continuous-time sigma-delta modulator with input transconductor is chosen which can limit the linearity performance of the system. A new method is proposed which has improved the AC linearity by almost 40dB. The system is implemented in a 0.7 µm CMOS process and with this technique, the linearity is comparable with the state-of-the-art designs.

Cardiovascular diseases are leading cause of deaths worldwide. With increasing graying population and limited health infrastructure there is a need for portable and implantable ECG devices to diagnose these diseases early on. In general an ECG device requires three or more electrodes, which need to be applied to the body via a gel, to obtain a satisfactory reading. This puts a constraint on the portability of the device. This thesis deals with designing a fully-integrated 10 bit analog front-end i.e. an instrumentation amplifier and an ADC, specifically, for a two-electrode ECG device. Integrated ECG read-out circuits have to deal with two challenges mainly viz. obtaining a high common-mode rejection ratio (CMRR) and integrating large time-constants on the chip. Firstly, all sources of interference which affect an ECG reading is studied. It is shown that for a portable and integrated read-out circuit, a high CMRR is obtained from the fact that the device will be floating and hence the circuit itself need not have a high CMRR. Existing techniques for integrating large time-constants are presented and compared. It is shown that these techniques either give rise to unpredictable time-constants and are non-linear near the required cut-o frequency or consume a lot of power from a system perspective. A novel mixed-signal feedback technique using a sigma-delta ADC has been proposed wherein the digital signal is scaled, integrated and fed back to the previous analog stage. The advantages of such a method are more control over the position of the cut-o frequency and higher linearity. The power consumption needed to implement such a technique is negligible. The circuit is designed in CMOS 0.35um I3T25 technology. The designed instrumentation amplifier reports the best SNR and 3rd highest Noise-Efficieny Factor (NEF). The linearity at the cut-o frequency is shown to be of 10 bits which is an improvement of 3 bits over existing techniques. The total static power consumption for the system is 66uW. The implementation of the time-constant consumes only 40nW of static power.

Low noise image sensors can see images by just a few photons have a wide application in both the scientific and economic fields. This thesis presents a design of a 16*16 pixels CMOS image sensor with a target noise level in the order of 0.5 electrons RMS in 0.18μm technology, which has a potential to catch a large amount of low light imaging market. First the novel 5T pinned photodiode low noise pixel is shown as well as the method cycling pMOS transistor well voltage between accumulation and inversion to shape the spectrum of flicker noise like white noise and to be decreased by oversampling. Then the readout circuitry with the sigma-delta ADCs and bidirectional digital counters are described. Correlated double sampling and oversampling technology are executed to decrease the quantization noise and thermal noise. At last, the system simulation, noise simulation results are given as well as the PCB test system.

Bridge sensors are widely used for accurate measurement of physical quantities such as temperature, pressure, strain or altitude. Such sensors require a low-noise, high-resolution and accurate readout system with high input impedance. In order to meet these requirements, conventional sensor readout systems use multiple stages which typically include a low-noise preamplifier, an anti-aliasing filter and a discrete-time (DT) sigma-delta modulator (ΣΔM). As a result, these systems involve several high-gain loops with total open-loop gain far exceeding the required closed-loop gain. This can lead to sub-optimal power dissipation and greater analog design complexity in design of a sensor readout system. In recent years, Gm-C continuous-time (CT) ΣΔMs have attracted a lot of attention due to their inherent anti-alias filtering, low power dissipation, high input impedance and high resolution. However, their use in precision applications such as bridge sensor readout is limited by the nonlinearity of the input stage. In this work, a new single-bit CTΣΔM topology is proposed that employs an identical nonlinear element in the feedback path along with a low pass filter to enable nonlinearity compensation and achieve high linearity. A feedforward Gm stage further enhances the nonlinearity compensation by increasing the effective loop-gain. This approach enables more than 60 dB improvement in the nonlinearity of the input transconductor stage of the CTΣΔM. A precision sensor readout circuit using the proposed CTΣΔM architecture is designed and implemented in 0.7 µm technology. The modulator achieves a resolution of 20 bits with a 22 nV/√Hz noise floor and an accuracy better than 10 ppm in post-layout simulations. It consumes 240 µA current from a 5 V supply. The resolution and accuracy of the CTΣΔM designed in this work is comparable to that of state-of-the-art readout systems but with lower power dissipation and lesser analog complexity. The proposed modulators achieves 10x better linearity and accuracy compared to the state-of-the-art Gm-C based CTΣΔMs, albeit at low frequencies, with significantly less noise and power dissipation.

Glucose sensors are useful for monitoring and control of blood-sugar concentration for diabetic patients. There are many challenges in their wide-spread use and effectiveness in control of the disease. This work is a step towards achieving in vivo continuous long-term glucose monitoring using the optical near-infrared based glucose sensing principle. The thesis investigates and arrives at an architecture for the readout circuitry of such a sensor system. The goal is that the realized CMOS chip together with the optical sensing devices realized in Silicon-on-Insulator technology will form a single-implantable solution. The advantage is the long-term monitoring due to non-usage of chemical reagents. The thesis work addresses the read-out circuit requirements for a photodiode as part of such a sensor. The design of a high-resolution current-input sigma-delta ADC is discussed which targets to achieve 16-bit resolution for a photo-diode signal in the range of 100nA-10μA. Various optimizations for specifications such as noise, accuracy and energy-efficiency both at circuit and system level are addressed. The chip has been realized in a TSMC 0.18μm process. The initial measurements show the functionality of the ADC and its performance using the test set-up developed. A proof of concept of the optical-electrical interface with a photodiode shows the application of the circuit.

This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread caused by lithographic inaccuracy. To minimize electrical phase spread, the TDC's front-end consists of a wide bandwidth gain-boosted transconductor. The transconductor's output current is then digitized by a phase-domain SigmaDelta modulator whose phase-summing node is realized by a chopper demodulator. To minimize the residual offset caused by the demodulator's switching action, the demodulator is located at the virtual ground nodes established by the transconductor's gain-boosting amplifiers. Measurements on 16 samples (within one batch) show that the TDC has an untrimmed inaccuracy of less than plusmn0.7degC (3sigma) over the military range (-55degC to 125degC).