· · · Institutional Repository

To meet traffic demand predictions, the global air traffic management (ATM) system needs to be changed. Several visions on future ATM operations exist. A commonality between the different visions is 4D Trajectory management. This function enables plan-based operation as opposed to the state-based approach of the present system. Plan-based operation enables the optimization of traffic flows by generating 4D trajectories. A part of the traffic flow generation process is scheduling. The research presented in this thesis focuses on these scheduling opportunities. In this research the scheduling opportunities for departure traffic at a runway are investigated. A study of the existing literature showed that the most common scheduling algorithms currently available can be divided into four categories: first come first served, brand-and-bound, greedy search and genetic algorithms. A simulation environment is designed for evaluation of the departure scheduling algorithms using various input parameters like traffic situation, airport map and algorithm. The four algorithm categories are evaluated on output aspects like delay and robustness of the schedule and are compared with the current method of traffic scheduling. The evaluation of the scheduling algorithms shows that the performance of the current method of scheduling departure traffic performs well in comparison with the tested algorithms. In case of no disturbances the genetic algorithm performs slightly better than the current method, but the other algorithms do not have a better performance. When disturbances are taken into account, a bigger performance increase can be obtained by using scheduling algorithms.

Vertigo Flight Simulation is a company located in The Netherlands with its mission being to design, produce and sell low cost flight simulation devices to all levels of the flight training market. One of the products which is developed by Vertigo Flight Simulation is the Vertigo P-2 Trainer. The P-2 Trainer is a fixed-base flight simulator capable of simulating single and twin engine piston aircraft with Flight & Navigation Procedures Trainer Type II (FNPT II) approved aerodynamic and engine models. One important feature which is not yet available for the P-2 Trainer is an Automatic Flight Control System (AFCS) which contains an AutoPilot (AP) and a Flight Director (FD). This system is developed, which includes research, design and implementation, in this thesis by the author as its Master of Science (MSc) Thesis Project for obtaining his Engineering Degree in Electrical Engineering, specialization Avionics. An Automatic Flight Control System has two main functions: the first is to control the aircraft without the need for the pilot to fly the aircraft and the second function is to present the pilot with suggestions how he or she should control the aircraft to follow a certain, by the pilot chosen, attitude, course, altitude or flight plan / flight path. During research, it was found that Automatic Flight Control Systems are basically all designed and based on classical control system theory: inner-loops are used to control the aircraft (these are called the control loops) and outer-loops are used to guide the aircraft (these are called the guidance loops). The problem initially found in implementation of the system was to tune the various inner- and outer-loop gains to give desired aircraft-responses. This problem was overcome by approaching the problem from the classical control system theory point of view. Because the P-2 Trainer is developed with flexibility in mind, it uses a modular design to be able to easily change the aerodynamic aircraft-model and instruments to simulate a new type of aircraft. Because of this design, the Automatic Flight Control System must also be a flexible system. Since the method of simulation, testing and tuning the system is extremely time absorbing, a method will be presented to let the system adapt itself every time a new aerodynamic model is loaded in the flight simulator.

In this thesis we consider the application of multi-cores in safety critical real-time systems, especially avionics. In our literature study we extract two major challenges. Firstly the unpredictability that comes from the concurrent access of shared resources (especially the on-chip interconnect) must be dealt with. To address this we propose to extend the concept of partitioning which provides fault containment, in combination with resource reservation at design time. The second challenge is to optimize the hardware usage without compromising on the determinism inherent to static mapping and scheduling. We propose mode-based mapping to deal with this, which allows to switch between multiple static schemes. We capture these concepts in a simple formal model. Mode-based mapping is enabled by task migration. The transfer time of tasks must be bounded, which requires guarantees on the Quality-of-Service (QoS) offered by the interconnect. Modern multi-cores feature Networks-on-Chip (NoC), which are packet-switching interconnects consisting of links and routers. Key to deterministic behaviour of NoCs this is avoiding contention, this can be achieved with flow control and buffering strategies based on resource reservation. We propose the use of transient modes to control the changes between the different modes in a NoC. To evaluate different transfer methods we conducted a number of experiments on a 64-core processor that features a NoC. The experiments show that both data prefetching from the shared cache and the programmer accessible networks are suitable for deterministic task transfer. The former is twice as fast but the number and size of shared data objects must be limited because timing analysis of large coherent shared caches is not feasible. For all methods the maximum deviation from the mean values is constant (0,4 us), and the standard deviation is under 1/2 % of the total transfer time. This shows that these methods are deterministic and that a tight bound on the transfer time can be determined. We conclude that private caches and scratchpads are suitable memory architectures for real-time systems, which can be supported by message passing and explicit communication through small shared memory regions. Mapping traffic at design time avoids contention, and isolation of traffic at the transfer level offers additional fault-tolerance. We propose a number of improvements for the transfer methods considered in our experiments that will enable guarantees on QoS. Our experiments confirm the feasibility of the proposed concepts.