· · · Institutional Repository

Hardware verification is a very important step of system design. Various techniques are used for this purpose one of which is hardware emulation. Hardware emulation is a very efficient and flexible technique with high speed performance in comparison to other approaches. Emulation using programmmable hardware can provide a very fast and feature rich debugging environment for system verification. The size and the complexity of todays Integrated Circuit designs though may exceed the size of the programmable devices used by the emulator in order to map the design under test. Therefore, in order to create a prototype of emulator and the design under test, we need to find a way to partition the whole design on the several programmable devices of the emulator. This thesis addresses the problem of design partitioning for a custom emulator using the flatten netlist of the design and implementing a variation of the graph partitioning algorithm of Fiduccia–Mattheyses. The tool that we have developed extends the Fiduccia–Mattheyses algorithm while retaining the linear runtimes that the algorithm has in order to fit the various constraints of a custom emulator. We extensively test the various parameters of the algorithm and the impact they have on the performance of the tool and report the behavior and the improvement on the number of cutted nets from an arbitrary and a manually clustered partition. In both cases the improvement is more than 50% upon the initial cut.

In recent years, exciting new low-power design methods have been introduced, such as: multiple supply voltages, body bias techniques and power shut-off. In order to use these low power design methods, strict requirements for both libraries and tools are needed. An additional challenge is the introduction of more accurate characterization models for newer technologies (current source models like ECSM and CCS). This has made the task of library checking a serious issue that needs to be automated. The main part of this thesis presents a checker tool that is used to verify the consistency of the different library formats (views) in standard cell libraries. The layout consistency checker in our tool checks the consistency of the layout of pins between GDSII and LEF library views; we devised a new algorithm,Grid Formation and Centre Inclusion, for this checker. The tool also verifies the pin consistency and availability of cells across other library formats, such as: Verilog and Liberty. The tool was tested using different technology libraries (such as 90nm and 40nm), provided by different vendors (such as GLOBALFOUNDRIES); multiple interfacing errors were caught using our library checker tool. A second part at the end of the thesis shows experiments with some of the low-power design techniques used during the design of a digital block, using -for implementation- standard cells from one of the libraries that have been checked with the library checker tool. Benefits of using these techniques are evaluated and trade-offs are discussed. Power-Shut Off (PSO) design technique proved to be the most effective in reducing power consumption, with power savings that reached 20%.

This project suggest a process to Design for Lovable Sevices, which are offers that promote and allow users to construct an emotional bond. The goal is to provide Fjord, a Service Design Consultancy, with a new approach to design services that aim for user engagement and retention. The challenge derives from two aspects: The growing number of Digital Service offers, which gives the users the possibility to easily switch between service providers resulting in detachment. It is then hard for services providers to sustain their business on the long-term. On the other hand, Fjord believes in designing services that users fall in love with, which would enable constructing emotional bonds aiming for user retention. The project resulted in a design process and supporting tools that Fjord can use to create Lovable Services, bringing the company’s mind-set into their daily acting. Additionally, the project suggest an implementation strategy to implement the suggested changes inside the company.

The design and realization of complex buildings requires multidisciplinary design collaboration from early on in the design process. The intensive use of digital design environments in this process demands new knowledge and skills from the involved players including integrating and managing digital design data, developing custom design tools, and utilizing visualization and rapid prototyping techniques. In order to prepare our students for these evolving practices we have developed a multidisciplinary collaborative design studio, named XXL, where student teams work in groups and each students claims a role: architectural design, structural design, digital design, construction and cladding design, and process management. In this paper, we describe the studio, discuss the contributions of the Digital Design Manager, and relate these contributions to design education and practice.