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This thesis presents a power analysis for various arbitration schemes. We chose variations on the round-robin and time-division multiplexing schemes as our arbiter configurations. The arbiters were implemented with 90 nm low-power standard cell libraries from TSMC, and gate-level power extraction was performed. Clock-gating was optionally introduced during synthesis. We then contrasted the power dissipation for the different arbiters and showed that no single arbitration scheme performs well in terms of power dissipation under all load conditions. We also analyzed why the power dissipation curve of a round-robin arbiter shows a point of maximum inflection. This thesis implements also a multiprocessor system-on-chip design. Such designs can offer significant power savings over traditional uniprocessor designs. We analyzed the power of such a system, and showed how it can be constructed in both hardware and software.

Ultra Wideband (UWB) radio represents a promising way of communication for low power applications in interference-prone environments. For achieving a low power solution the digital baseband architecture needs to be carefully optimized to reduce the total power consumption. Particularly for the computationally intensive synchronization phase that detects UWB signals in noisy input data, low-power correlation architectures are crucial. In this thesis, a low power exploration is performed at different levels of abstraction. The architecture of the correlator is designed and optimized to support several modes of operations efficiently. Deviating from a memory dominant design, our improved architecture is based on circular register buffer and a corresponding partitioning method. The impact of biased representation is studied in terms of power and area. The possibility and the influence of voltage reduction is also investigated by changing to the Lvt cells and pipelining the critical path. Our design is implemented and simulated in a Cadence based design flow, targetting 90 nm process technology. Experimental results show that, compared to 'standard' design, the proposed correlator can achieve up to 2x total power reduction with only 10\% overhead on area.

UWB-FM is a low-complexity ultra-wideband (UWB) communication system designed for short-range, low- and medium-data-rate wireless applications such as the personal area network (PAN). These applications often require simple, integrated receivers with low power consumption. Most of previous work utilized delay-line demodulators for UWB-FM detection. This coherent detection method offers the best performance in general but is not necessarily power-efficient. Reported power consumption was around 20 mW for a 2 GHz RF bandwidth. The goal of this research is to explore the possibility of reducing power consumption of a UWB-FM receiver by exploiting the super-regeneration principle. As a result, a fully integrated super-regenerative receiver in IBM 90-nm RF CMOS technology is designed to detect 500 MHz bandwidth UWB-FM signals at 4.5 GHz. Circuit simulations show that a receiver sensitivity of -82.2 dB is attainable for a 100 kbps baseband data-rate and 10^{-6} bit-error-rate. The whole receiver draws an average of 2 mA from a 0.9 V supply. This work is, according to the author's knowledge, the first time the super-regeneration principle is used for UWB-FM detection. The 1.8 mW power dissipation is also by far the smallest among UWB-FM receivers reported in the literature. In addition, the contribution of this work includes an innovative optimization of the quenching waveform for WBFM detection and a novel low-power driven design procedure for LNAs. In conclusion, super-regenerative receivers are promising for short-range, low-data-rate UWB-FM applications, due to their simplicity and low power-consumption.

The required product is a wireless indoor climate sensor. It is an autonomous sensor that transmits several parameters concerning its environment wirelessly. The product will be used to demonstrate a number of energy efficient sensors. The electronic instrumentation department at Delft University of Technology developed these sensors in association with NXP. Since the desire to communicate information wirelessly in an energy efficient way existed, several options could be explored. First a wireless protocol had to be chosen. Thereafter, a hardware solution had to be found in order to implement the chosen protocol. Lastly, the information had to be displayed on a computer screen. This thesis investigates six wireless protocols that can transmit information. The investigated protocols are Bluetooth, ZigBee, Rubee, UWB, Z-Wave and the well known Wi-Fi. In order to choose the right option, several criteria were set up. First of all, the system had to be entirely wireless. Therefore, the power consumption had to be as low as possible. Moreover, the program of requirements stated that the transmission distance had to be at least five meters. After searching for suitable wireless protocols for this assignment, the hardware had to be chosen. The SX1212, XBEE series II, ATmega128RFA1 and CC430xxxx were found as potential solutions. The same criteria that were subjected to the wireless protocols were applied to these hardware solutions as well. Furthermore, the ease of hardware implementation was added as well as the ease of software implementation. Additionally, the knowledge available at EEMCS about these solutions was appended to the criteria. The measurements had to be displayed after setting up the wireless communication. The measurements could be displayed on a website, an app or a computer screen. The measurements could have been stored locally as well as externally. Safety is one of the criteria used to choose a display solution. This was why locally storing the measurements was preferred. However, the recent popularity for apps was a criterion for choosing the method of displaying the information as well. The ZigBee solution was chosen, because it was most suited for this project. Rubee, UWB and Wi-Fi were abandoned, because those protocols do not meet the specifications. ZigBee uses less power than Z-Wave and therefore, is chosen above Z-Wave. The fact that former researchers encountered problems while setting up a connection between two Z-Wave modules was added to the argumentation. Bluetooth can have either a short range or a high outputpower to transmit. Since the “short range” was considered too short, Bluetooth was abandoned as well. Moreover, ZigBee had been developed to transmit a low amount of data in a low power consuming way. Hardware had to be chosen after finding a suitable protocol. The XBEE series II was chosen from the hardware solutions. A low amount of data had to be sent and the XBEE series II was the least power consuming of these solutions while sending a low amount of data. Moreover, the XBEE series II was the easiest to implement. There were several options to display the received data. Since the data had to be received by a computer, displaying it on a computer screen was chosen. The data was displayed in the console in which the program was written. Moreover, an internet connection is not mandatory. However, it was chosen to develop an app as well. This is because an app can be viewed anywhere at any time. The current running through the system was measured in order to check if the requirements were met. The system appeared to have an average current consumption of 50.8μA. This consumption would be sufficient for the system to run autonomously for a year. Furthermore, it was necessary to check if the system was able to transmit over at least 5 meters, since the program of requirements stated this demand. The measurements showed that the system was able to transmit over 40 meters, which was enough.

With the completion of the MIST1431 multi sensor IC a demonstrator developed by the Electronic Instrumentation Laboratory of Delft University of Technology and NXP, a demonstrator that shows the capabilities of the MIST chip was needed. This thesis describes the implementation of the control unit, which has to control the MIST chip and wireless communication module residing in the demonstrator. Temperature and relative humidity had to be transmitted wirelessly at low power consumption. A method of analysis and assessment of the different methods and hardware was developed. Then a suitable controller was chosen: the LPC1114. After choosing the controller, a study about the functionalities of the controller was done. Software was designed and written. Finally measurements were taken proving the functionalities of the demonstrator. Testing showed that the demonstrator is capable of sending its measurements once per second to a computer while using a mean of 50.807μA. The result is that the demonstrator meets its requirements.

This thesis discusses the theory, architecture and circuit design and measurements of an ultra-low-energy prototype interface circuit for a resonant gas sensor in standard 0.35-μm CMOS technology. A transient measurement method is used here. The resonant sensor is driven at a frequency close to its resonance frequency by an excitation source that can be intermittently disconnected causing the sensor oscillation amplitude to decay exponentially. From the ring-down signal, the frequency of the freely oscillating sensor and the quality factor are obtained. Test chips are fabricated to measure the resonance frequency and quality factor of the resonant sensor using ring-down measurement approach. The obtained results(resonance frequency and quality factor) show good consistency compared with what we obtained using an alternative approach (impedance analysis). The circuit consumes an energy of 237nJ per measurement.

Analog IC Techniques lor Low-Voltage Low Power Electronics addresses many very important, but recent, techniques which enable electronics to operate at a low supply voltage and consume a minimum amount of power. Apart from investigations at the device, circuit and system levels, the book provides a wealth of practical implementations, many worked out in silicon realizations. The book is intended for both the professional designer of low-voltage low-power analog integrated circuits and the graduate student in this specialized branch of electronics.

Micro-Digital Sun Sensor (μDSS) is a sun detector which senses the respective angle between a satellite and the sun. It is composed of a solar cell power supply, a RF communication block and a CMOS Image Sensor (CIS) chip, which is called APS+. The paper describes the implementation of a prototype of the μDSS APS+ processed in a standard 0.18μm CMOS process. The μDSS is applied for micro or nano satellites. Power consumption is a very rigid specification in this kind of application, thus the APS+ is optimized for low power consumption. This character is realized by a specific pixel design which implements profiling and windowing during the detection process. The profiling is completely fast and power efficiently by a “Winner Take ALL (WTA)” principle. The measurement results shows that the APS+ achieves a reduction of power consumption by more than a factor 10 compared to state of-the-art. Besides the low power consumption, the APS+ also proposes a quadruple sampling method which improves thermal noise with 3-T Active Pixel image Sensor (APS) structure.

Investigation on Tile-Based Rasterization on Mobile Devices. External traffic on mobile devices is a major part of power consumption. We start with a critical evaluation of previous work on Tile-Based Rasterization where software was used to reduce external traffic. The added software is now killing the performance of the microprocessor. We propose Tile-Based Rasterization alternative which aim to reduce software workload while keeping external traffic low.

Event-driven wireless communication is a promising concept that presents new challenges to designers. For an event-driven transmitter, achieving high efficiency under the condition of ultra-low-power (ULP) consumption is one of the most critical tasks. It places emphasis on the importance of carrier generation. This is the motivation of this thesis, which mainly focuses on designing a ULP digitally-controlled oscillator (DCO) for event-driven transmitters.

Ultra-wideband (UWB) is a promising radio technology which is well suited to low power short-range wireless applications. At Holst Centre/imec, there is a research program on the design and implementation of ultra low power, Impulse Radio-UWB (IR-UWB) wireless systems suitable for audio streaming and real time localization systems. Some key technology challenges for IR-UWB systems are Direct Current (DC) power consumption, Link-budget and Quality of Service (QoS). The first part of this thesis focuses on measurement of DC power consumption; transmit output power and spectrum using the IR-UWB transmitter. As the hardware supports several modes, an automated measurement setup with programmable parameters has been created. In the second part, a mathematical model for the preamble and Start of Frame Delimiter (SFD) detection stages of the receiver operation is provided. This part of the receiver is a critical one and is challenging for IR-UWB type of signals due to the low transmit power. A method to estimate the signal to noise ratio (SNR) per pulse from the output of the preamble detection block is proposed. A theoretical approach for setting the threshold for SFD detection is described. It is shown through simulations that this method of threshold setting provides a significant improvement in receiver performance.

In recent years, exciting new low-power design methods have been introduced, such as: multiple supply voltages, body bias techniques and power shut-off. In order to use these low power design methods, strict requirements for both libraries and tools are needed. An additional challenge is the introduction of more accurate characterization models for newer technologies (current source models like ECSM and CCS). This has made the task of library checking a serious issue that needs to be automated. The main part of this thesis presents a checker tool that is used to verify the consistency of the different library formats (views) in standard cell libraries. The layout consistency checker in our tool checks the consistency of the layout of pins between GDSII and LEF library views; we devised a new algorithm,Grid Formation and Centre Inclusion, for this checker. The tool also verifies the pin consistency and availability of cells across other library formats, such as: Verilog and Liberty. The tool was tested using different technology libraries (such as 90nm and 40nm), provided by different vendors (such as GLOBALFOUNDRIES); multiple interfacing errors were caught using our library checker tool. A second part at the end of the thesis shows experiments with some of the low-power design techniques used during the design of a digital block, using -for implementation- standard cells from one of the libraries that have been checked with the library checker tool. Benefits of using these techniques are evaluated and trade-offs are discussed. Power-Shut Off (PSO) design technique proved to be the most effective in reducing power consumption, with power savings that reached 20%.

In this dissertation, we address low-power high performance 3D graphics accelerator architectures. The purpose of these accelerators is to relieve the burden of graphical computations from the main processor and also to achieve a better energy efficiency than can be achieved by executing these computations on the main processor. Since external data traffic is a major source of power consumption and because usually the rasterization stage of the 3D graphics pipeline requires the highest amount of data traffic, in this dissertation we especially focus on this stage of the graphics pipeline. Another reason for focusing on the rasterization stage is that it requires more processing power than the other stages because the operations are pixel-based. A promising technique to reduce the external data traffic in the rasterization stage of the graphics pipeline is tile-based rendering. This technique decomposes a scene into tiles and renders the tiles one by one. This allows the color components and z values of one tile to be stored in small, on-chip buffers, so that only the pixels visible in the final scene need to be stored in the external framebuffer. Tile-based accelerators, however, require large scene buffers to store the primitives to be rendered. While there have been studies related to the tile-based rendering paradigm for high performance systems, we are specifically discussing the suitability of tile-based 3D graphics accelerators for low-power devices. In order to evaluate various low-power 3D graphics architectures we first present GraalBench, a set of 3D graphics workloads representative for contemporary and emerging mobile devices. Furthermore, we propose several scene and state management algorithms for tile-based renderers. Thereafter, we analyze the performance of tile-based renderers compared to that of traditional renderers and we also determine the influence of the tile size on the amount of the data-traffic required for the rasterization stage of a tile-based renderer. In order to reduce even more the data traffic between the main memory and graphics accelerators, and to exploit the high temporal and spatial locality of texture accesses, we have also investigated several cache structures. Our results show that the proposed algorithms for tile-based renderers can effectively decrease the data traffic and computational requirements for the rasterization stage of the 3D graphics pipeline.

A new prototype adaptive deformable mirror for future AO-systems is presented that consists of a thin continuous membrane on which push-pull actuators impose out-of-plane displacements. Each actuator has ±10μm stroke, nanometer resolution and only mW’s heat dissipation. The mirror’s modular design makes the mechanics, electronics and control system extendable towards large numbers of actuators. Models of the mirror are derived that are validated using influence and transfer function measurements. First results of a prototype with 427 actuators are also presented.

We present a design for a manipulator that is intrinsically mechanically safe, i.e. it can not cause pain (let alone damage) to a human being even if the control system has a failure. Based on the pressure pain thresholds for human skin, we derive a pinching safety constraint that limits the actuator torque, and an impact safety constraint that results in a trade-off between mass and velocity. To fulfill all constraints, the manipulator requires a spring balancing system that counteracts gravity in all configurations of the manipulator. This allows the use of extremely low-power DC motors (only 4.5 W). Thanks to the torque and speed limitations of these motors the manipulator is indeed intrinsically safe, yet still capable of moving a useful payload of 1.2 kg over a distance of 0.8 m in 1.5 s.

A digital sun sensor is superior to an analog sun sensor in aspects of resolution, albedo immunity, and integration. The proposed Micro-Digital Sun Sensor (µDSS) is an autonomous digital sun sensor which is implemented by means of a CMOS image sensor, which is named APS+. The µDSS is designed specifically for micro-satellite application which addresses for low power and high accuracy. The APS+ significantly reduces the power consumption by a profiling method and obtains low noise by a quadruple sampling method. Measurement results show that the µDSS achieves an accuracy of 0.01º with 21mW@10fps, which is 10 times less than the state of the art.

This thesis describes the design of a front-end application-specific integrated circuit (ASIC), which will be put into the tip of a miniature ultrasound probe for 3D Trans-Esophageal Echocardiography (TEE). To enable 3D TEE, a matrix piezoelectric ultrasound transducer with more than 2000 elements will be used. Since a gastroscopic tube cannot accommodate the cables needed to connect all the transducer elements directly to an imaging system, local channel-count reduction is necessary. The main task of the ASIC is to provide appropriate signal conditioning in the tip of the probe to achieve channel-count reduction. The main goal of this thesis work is to design such an ASIC using simple, low-power circuits, while still maintaining good image quality. In addition to the electronics design, the interconnection between the matrix transducer and the ASIC is another important parallel research topic.