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Software systems are getting larger and more complex. It takes therefore more time and money to maintain these systems. The maintenance effort is strongly related to the quality of the implementation during the development phase. Providing qualitative numbers to developers about their previous im- plementations could help increase the quality of their next implementation. In this thesis an approach is presented both for gathering internal software qual- ity metrics that are related to a system’s maintainability and also for extracting information from these metrics. The extracted information is then returned as feedback to the development team to give them the ability to improve their source code. This in turn will increase the virtuous circle of improved main- tainability which again results in better software quality overal. This is done via a self-made feedback reporting tool which is described in detail. Three projects have been followed both before and after developers got access to our feedback mechanism. Afterwards, we evaluate the situations.

Software systems make up an important part of our daily lives. Just like all man- made objects, the possibilities of a software system are constrained by the choices made during its creation. The complete set of these choices can be referred to as the software architecture of a system. Since the software architecture of a system has a large influence on what can, and cannot, be done with the system, it is important to regularly evaluate this architecture. The purpose of such an evaluation is to create an overview of the strengths and weaknesses of the software architecture, which can then be used to decide whether each weakness is accepted or should be addressed. There is a wide range of software architecture evaluation methods available which can be used to investigate one or more quality aspects of a software architecture. Most of these methods focus on the initial design of the software architecture, there are only a few which specifically target the implemented architecture. Looking at the design alone is not problematic if design and implementation are in sync, but unfortunately there are many occasions in which these two architectures deviate. Moreover, some systems are even built without an initial design at all. In addition, earlier research shows that software architectures are not regularly evaluated in practice, despite the availability of these methods. The reason for this is that the initial effort to start performing software architecture evaluations is considered to be too high for project teams. The goal of this thesis is to lower this initial investment by providing an overview of concrete evaluation attributes, as well as the definition of software metrics that can be used to evaluate these attributes. Our global research approach is that of “industry-as-a-lab”. During our research we have closely collaborated with the Software Improvement Group to design solutions, and to test these solutions on real-world cases. To be able to provide concrete advice we must focus on only a single quality attribute; in this thesis we choose to focus on the maintainability quality attribute of a software system. Following from our goal the research in this thesis is composed of two parts. The focus of the first part is on the identification of architectural attributes that can be used as an indicator for the maintainability of a software system. The result of mining over 40 evaluation reports, interviewing experts, and a validation with various experts is a list of 15 architectural attributes which experts consider to be indicators for the maintainability of a software system. To augment the opinion of the experts we used theories from the field of cognitive psychology to extend an existing model for architectural complexity. This extended model makes it possible to explain why each of the found attributes influence the maintainability of a software system. Based on the attributes and the model we developed a lightweight sanity-check for implemented architectures. This check consists of 28 questions and 28 actions divided over five categories. A person familiar with a system can use this check to get an initial overview of the status of their system within a day, and needs less effort to repeat this evaluation later on. In the second part of our research we focus on the design and validation of metrics related to two quality attributes: balance and independence. These two attributes are related to two of the major building blocks of an implemented architecture; the definition of the components of the system and the relationship these components have with each other. In the ideal case a system is decomposed into a limited set of components on the same level of abstraction, while the dependencies between these components is limited. To quantify the number of components and their level of abstraction we define the Component Balance metric. This metric takes the number of components of a system and the distribution of the volume of the system over these components and outputs a score between zero and one. Interviews with experts and a case-study show that the scores of this metric correlates with scores given by experts. The quantification of the dependencies between the components is done by a Dependency Profile. In such a profile, all code within a component is divided into one of four categories depending on whether a piece of code is dependent upon by, or depends on, code in other components. A large-scale experiment shows that the percentage of code in these categories is correlated with the ratio of local change within a system. Both metrics are implemented in practice to evaluate the usefulness of these two metrics within the context of the evaluation of implemented architectures. The results of a structured observation of experts using the metrics during a period of six months and interviews with 11 experts show that there is room for improvement, but that the two metrics are considered to be useful within this context. The combination of different research methods such as interviews, case-studies, empirical experiments and grounded theory, augmented by experiences taken from practice have lead to research results which are both valid and useful. In this thesis we lower the initial effort needed to start performing architectural evaluations by show- ing which concrete attributes should be taken into account, and how these attributes could be evaluated in a continuous manner. Additionally, we define and validate met- rics for two of these attributes, and show that experts find these metrics useful in the evaluation of implemented architectures within practice.

The present Low Voltage (LV) grid, which until recently was mainly composed of passive electrical components (consumers), is being gradually overrun by active electrical components (prosumers), who not only consume but also generate and share power locally. This development is introducing changes in the operational dynamics of the LV grid that could result in voltage stability problems and the violation of infrastructural constraints if not well managed. A re-design of the present LV grid is, therefore, imperative to enable it meet these new requirements. This thesis was aimed at studying the influence of topological metrics on the operational performance of the LV grid in view of current developments in energy consumer behaviour with a view to proposing the topological changes and/or modifications in network architecture that would yield optimal outcomes. We modelled the present LV grid as a radial network, and compared it to three other network models -random, small-world and scale-free networks- under different loading scenarios. We proposed novel structural and operational metrics that are suitable for the LV grid, and analysed the networks in terms of these metrics. We also compared their robustness under different attack scenarios and demonstrated the correlation between the structural and the operational metrics, thus, identifying important structural metrics that need to be optimized to improve the future LV grid performance. Finally, we then investigated the possible modifications of the radial network model of the present LV grid that would yield similar results. The results highlighted the structural weaknesses of the present LV grid under futuristic and simultaneous loading conditions and presented the scale-free model as the most suitable architecture for the future LV grid as it out-performed all the other network models under similar loading conditions. They also showed that the insertion of additional links at critical positions in the radial network could achieve similar results. We therefore proposed this structural modification as a more cost-effective approach to improved operational performance of the LV grid.

Automated testing is a basic principle of agile development. Its benefits include early defect detection, defect cause localization and removal of fear to apply changes in the code. Therefore, maintaining high quality test code is essential. This study introduces a model that assesses test code quality by combining source code metrics that reflect three main aspects of test code quality: completeness, effectiveness and maintainability. The model is inspired by the SIG Software Quality model which aggregates source code metrics into quality ratings based on benchmarking. To validate the model we assess the relation between test code quality, as measured by the model, and issue handling performance. An experiment is conducted in which the test code quality model is applied on 18 open source systems. The correlation is tested between the ratings of test code quality and issue handling indicators, which are obtained by mining issue repositories. The results indicate a significant positive correlation between test code quality and issue handling performance. Furthermore, three case studies are performed on commercial systems and the model's outcome is compared to experts' evaluations.

Heterogeneous System Development needs Hardware/Software Partitioning performed early on in the development process. In order to do this early on predictions of hardware resource usage and delay are necessary. In this thesis a Quantitative Model is presented that can make early predictions to support the partitioning process. The model is based on Software Complexity Metrics, which capture important aspects of functions like control intensity, data intensity, code size, etc. In order to remedy the interdependence of the software metrics a Principal Component Analysis performed. The hardware characteristics were determined by automatically generating VHDL from C using the DWARV C-to-VHDL compiler. Using the results from the principal component analysis, the quantitative model was generated using linear regression. The error of the model differs per hardware characteristic. We show that for flip-flops the mean error for the predictions is 69%. In conclusion, our quantitative model can make fast and sufficiently accurate area predictions to support Hardware/Software Partitioning. In the future, the model can be extended by introducing extra software metrics, using more advanced modeling techniques, and using a larger collection of functions and algorithms.

Static analysis techniques provide a means to detect software errors early in the development process, without actually having to run the software that is being analyzed. These techniques are common for statically typed languages and have found their way into IDEs such as Eclipse and Visual Studio. However, applying the same techniques to dynamically typed languages is much less common. Tool support is less mature and the amount of published research is relatively small. For this project, we design and build a static analyis tool for JavaScript code. We start by giving background information on relevant parts of the JavaScript language, followed by a survey of existing tools and research. In the design of our analysis tool, we achieved a clear separation of responsibilities between the different modules for parsing, analysis, rule definition and reporting. The level of detail in the default reporter makes our tool an ideal candidate for integration in a JavaScript IDE. On the other hand, our tool is also suited for batch analysis of large code collections. To validate our tool, we set up an experiment in which we ran our analysis tool on two large collections of JavaScript code: one from a repository of open source JavaScript packages, mostly for server-side use; another one gathered from client-side code on a large number of popular websites. We present high-level global results as well as more detailed results for selected projects and websites.

A lack of cohesion is often associated with bad software quality, and could lead to more changes and bugs in software. In this thesis the impact of cohesion on the change-proneness of Java interfaces is investigated. Showing the existence of a relation between these concepts can lead to better change prediction models that can support software developers in defect prediction and prevention tasks. An empirical study is performed on several open source projects to test three hypotheses. The first hypothesis investigates whether cohesion metrics correlate with the number of fine-grained source code changes. The results of the correlation analysis show a correlation between two cohesion metrics and the number of changes in Java interfaces. The confounding effect of class size is a possible explanation for the correlation between the cohesion metrics and the number of fine-grained changes. This idea is investigated through the second hypothesis, which studies the correlation between the cohesion metrics and interface size metrics. The hypothesis is accepted for the same two metrics. The third hypothesis of this thesis tries to answer whether cohesion metrics can improve change prediction models based on size. By performing three different experiments with multiple classification algorithms, we have found no evidence that supports the final hypothesis. Concluding, cohesion metrics can be used to predict changes in source code. However, they are not better predictors than size metrics, and we have found no evidence to support the idea that they can improve change prediction models based on size.

Nowadays, for the defense and security community, it is of prior importance to classify threats that are merged in a background while at the same time understanding the context of the entire scene. Traditional TV and Infra-Red (IR) cameras allow for an easy context understanding by providing valuable background and scenery information. Unfortunately, they typically do not allow a human observer to detect and classify semi-hidden targets. This study investigates the added value of the combined use of laser range gated viewer (GV) and IR camera to solve semi-hidden target recognition. To this end, an algorithm is developed to fuse GV and IR images based on a weighted averaging technique and employing existing multi-resolution image representation schemes. Our best fusion method for semi-hidden target recognition is selected from all methods considered by using an Image Quality Metric (IQM) combined with an accurate saliency metric. Both metrics are validated using human conspicuity experiments. For very complex scenarios, we additionally designed a background dimming algorithm that dims the scene either entirely or partially based on the context of the scene (contextual) or locally around the threat, while keeping the threat itself undimmed. The optimal combination of fusion method and amount of dimming is determined by means of a second human conspicuity experiment. In a final human experiment, we tested if moving objects influence the preferred amount of dimming. Our work shows that fusing GV into IR scenery images improves the human recognition task on semi-hidden targets. Moreover it demonstrates that a relatively simple pixel-based approach with a PCA-based weighted fusion scheme is the optimal fusion method among those considered. Additional results show that, especially, so-called contextual dimming improves target recognition in very complex scenarios and that moving objects require slightly more dimming in order to obtain the required performance.

In an earlier paper we showed, that perceived quality of channel zapping is related to the perceived quality of download time of web browsing, as suggested by ITU-T Rec.G.1030. We showed this by performing subjective tests resulting in an excellent fit with a 0.99 correlation. This was what we call a lean forward experiment and gave the rule of thumb result that the zapping time must be less than 0.43 sec to be good ( > 3.5 on the MOS scale). To validate the model we have done new subjective experiments. These experiments included lean backwards zapping i.e. sitting in a sofa with a remote control. The subjects are more forgiving in this case and the requirement could be relaxed to 0.67 sec. We also conducted subjective experiments where the zapping times are varying. We found that the MOS rating decreases if zapping delay times are varying. In our experiments we assumed uniformly distributed delays, where the variance cannot be larger than the mean delay. We found that in order to obtain a MOS rating of at least 3.5, that the maximum allowed variance, and thus also the maximum allowed mean zapping delay, is 0.46 sec.

Because of their poor Business/IT alignment, many legacy systems lack the flexibility to support rapid changes to the business processes they implement, required by today's enterprises. Furthermore, after many years of maintenance, there is a need to manage their resulting increased complexity and maximize asset utilization through reuse. The third complicating circumstance is that these legacy systems cannot simply be replaced as it is too expensive and risky. For these three reasons, legacy systems are modernized towards a Service Oriented Architecture. This thesis presents a framework for performing an impact analysis of such a modernization. It supports the trade-off analysis, needed in the planning phase, for finding the optimal selection of modernization strategies and judging their yield. The impact is expressed through the estimation of, on the one side, the effort and, on the other side, the gain of the changes these modernization strategies entail. The thesis concentrates on one of the many types of changes in modernization -- the architectural and design changes to the software system. The presented framework structures current approaches to modernization in a set of class definitions, system model relationships and a process description. This is done according to the effort they produce, preparing them for its estimation. For this effort estimation, this thesis introduces a Rating Model for quantifying the modernization effort using the system models of the framework. This quantification is done through the identification of so-called Points of Modernization, a categorization of the modernization strategies and a set of effort indicator metrics. Based on this framework, this thesis also presents an experiment. For a subject legacy system, concrete approaches are shown for the instantiation of the framework models and the subsequent effort estimation is done using the indicator of Scattering. The analysis of the resulting effort and its relation to the gain show the optimal solutions for the modernization of the subject system. Concluding, this thesis discusses the feasibility of the approach and the future work such as more quantitative research on the rest of the effort indicators.

1. The purpose of the report is to investigate the transparency status in the gas systems and markets of Mediterranean countries, and to monitor the guidelines and recommendations on transparency contained in the MEDREG of Good Practice (GGP). The results of this analysis are presented in the report. 2. The purpose of this report is to give the possible assessment that would matter level of security of supply in EU and Spain, and to show how the Spanish Energy Supply risk was changing over years. By applying Energy Risk Metrics to the EU and Spain closer explanation about the factors that influence the energy system is found, and it is examined where and how the risk influence could be mitigated. The risk metrics is a great tool that could provide support to the future policy making policy making.

We performed an empirical study of the relation between technical quality of software products and the issue resolution performance of their maintainers. In particular, we tested the hypothesis that ratings for source code maintainability, as employed by the Software Improvement Group (SIG) quality model, are correlated with ratings for issue resolution speed. We tested the hypothesis for issues of type defect and of type enhancement. This study revealed that all but one of the metrics of the SIG quality model show a significant positive correlation with the resolution speed of defects, enhancements, or both.

This thesis presents circuit and interconnect design techniques and design flows that address the most difficult and ill-defined aspects of the design of ICs for high bit-rate applications. Bottlenecks in interconnect design, circuit design and on-chip signal distribution for high bit-rate applications are analysed, and solutions that circumvent these bottlenecks are presented. The methodologies presented indicate whether certain target bit-rates and operating frequencies can be realised in the IC technology available, and provide guidelines for further process optimisation to support todays and tomorrows high bit-rate circuit design. It should be noted that specific amplifier requirements such as noise and intermodulation distortion are not discussed in this thesis. The circuits analysed and designed in this thesis operate at bit-rates of 10 Gb/s and above. At such bit-rates, the impact of on-chip interconnect on circuit performance can be detrimental to the performance of the IC. Examples of this relate to the clock distribution of digital functions or the signal distribution inside cross-connect switches. The design of a cross-connect switch for optical networking is an excellent vehicle for the topics addressed in this thesis, since it involves many disciplines that are important for high bit-rate design. The block diagram of the cross-connect switch IC is shown in Figure 1.9. The analysis and design of the RF path of the cross-connect switch are described in Chapter 4. The RF path includes in- and output signal buffer circuits, the switch matrix and numerous transmission lines. To facilitate the joint optimisation of circuit and interconnect, simple but accurate interconnect models are needed in an early phase of the design. The interconnect configuration proposed in Chapter 2 of this thesis enables low loss, low crosstalk and well-controlled line characteristics (e.g. characteristic impedance and delay). This provides flexibility in the layout floorplan. The floorplan is usually not defined in the initial phase of an IC design. To understand the design and limitations of the RF circuits, a good understanding of the relationship between the transistor device metrics and circuit performance (e.g. bandwidth) is essential. This highlights the relevance of the extensive analysis of transistor device metrics presented in Chapter 3. The different subjects addressed in this thesis and how they relate to one another are illustrated in Figure 1. Most of this thesis is devoted to high bit-rate circuit design using advanced SiGe and InP HBT IC processes. The design of the cross-connect switch IC in Chapter 4 demonstrates the feasibility of a complex circuit operating at an aggregated bandwidth of up to 250 Gb/s in a SiGe process with 12 GHz fA. However, it also shows that significant improvements in circuit design and IC technology are needed to realise a similar function at 40 Gb/s per input. When higher supply voltages are used, other circuit topologies that may enable improved circuit bandwidths become feasible. Chapter 5 deals with the consequences of circuit design at supply voltages above the breakdown voltage of the transistor. Chapter 6 discusses the design of high bit-rate current-mode logic circuits (e.g. 40 Gb/s and higher). A PRBS generator is used as the test and demonstration vehicle. A design in an InP HBT technology is demonstrated which achieves record performance in terms of output bit-rate. In Chapter 7, a detailed analysis of LC-VCO circuits is provided. The fundamental maximum achievable oscillation frequency for various circuit topologies is analysed, and oscillator circuits are demonstrated to support the theories presented. Chapter 8 lists the conclusions and recommendations of this work. The most important conclusion is that three aspects have to be addresses in order to achieve maximum performance in high bit-rate circuits: IC technology, interconnect and circuit design. The IC technology must be optimised on the basis of fT, fA and fcross. The circuits and interconnect need to be optimized interactively, starting with the floorplan and continuing with the interconnect design. Topologies that extend performance beyond the previous state of the art have been proposed for several critical circuit functions.