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We provide an experimental proof of principle for a ternary multiplier realized in terms of the charge state of a single dopant atom embedded in a fin field effect transistor (Fin-FET). Robust reading of the logic output is made possible by using two channels to measure the current flowing through the device and the transconductance. A read out procedure that allows for voltage gain is proposed. Long numbers can be multiplied by addressing a sequence of Fin-FET transistors in a row.

We demonstrate single dopant implantation into the channel of a silicon nanoscale metal-oxide-semiconductor field-effect-transistor. This is achieved by monitoring the drain current modulation during ion irradiation. Deterministic doping is crucial for overcoming dopant number variability in present nanoscale devices and for exploiting single atom degrees of freedom. The two main ion stopping processes that induce drain current modulation are examined. We employ 500 keV He ions, in which electronic stopping is dominant, leading to discrete increases in drain current and 14 keV P dopants for which nuclear stopping is dominant leading to discrete decreases in drain current.

In this paper we present an original method for n-channel power MOSFET resistance extraction in the operation mode (RDS(ON)). The IDS=f(VDS) electrical characteristics measurements for the transistor and the Body-Drain junction are realized for the experimental determination and the extraction (by numerical analysis) of RDS(ON), respectively. Values of this resistance are extracted for different positive bias applied between the gate and the source (+VGS). Physicals parameters obtained from the numerical analysis are inspected, and results shows that the numerically analysed junction characteristic is in very good correlation with the electrical measurement

Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical tight-binding (TB) calculations, this technique can be used to understand the dependence of the source-to-channel barrier height (Eb) and the active channel area (Saa) on three important parameters: (i) the gate bias (Vgs), (ii) the temperature, and (iii) the FinFET cross-section size. The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) Saa and (ii) |∂Eb/∂Vgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nanometer width limit. Furthermore, theoretical investigation of the spatial current density reveals volume inversion in thinner FinFETs near the threshold voltage.

We report the characterisation of printed circuit boards (PCB) metal powder filters and their influence on the effective electron temperature which is as low as 22 mK for a quantum dot in a silicon MOSFET structure in a dilution refrigerator. We investigate the attenuation behaviour (10 MHz–20 GHz) of filter made of four metal powders with a grain size below 50 μm. The room-temperature attenuation of a stainless steel powder filter is more than 80 dB at frequencies above 1.5 GHz. In all metal powder filters, the attenuation increases with temperature. Compared to classical powder filters, the design presented here is much less laborious to fabricate and specifically the copper powder PCB-filters deliver an equal or even better performance than their classical counterparts.