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Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms

Author: Van Wijnen, P.A.
Mentor: Gaydadjiev, G.N.
Faculty:Electrical Engineering, Mathematics and Computer Science
Department:Microelectronics & Computer Engineering
Type:Master thesis
Keywords: Hardware Accelerator · Pattern Recognition Algorithm · FPGA · Parallel Computing
Rights: (c) 2009 Van Wijnen, P.A.


This thesis presents a feasibility analysis for hardware acceleration of the pattern recognition algorithms used by the Media Knowledge Engineering department at the Delft University of Technology. The feasibility analysis is conducted on a number of different algorithm classes. The Parzen Window algorithm appeared to be the most suitable option for acceleration when recongurable hardware is considered. The reason for this is that the Parzen Window consists of independent calculations that can be computed in parallel. It can be computed by execution of Custom Configured Hardware Units (CCU) in Field Programmable Gate Arrays (FPGAs). The feasibility analysis presented, gave insight in the question whether it is useful to implement these kind of algorithms in hardware. Our results showed that algorithms that have independent calculations and thus are able to be executed in parallel are strong candidates for hardware implementation, certainly when the design can be executed with integer calculations. Integer calculations reduce the complexity of hardware implementation, require smaller area on the FPGA, reduce the bandwidth of the calculations and can be computed faster than their floating point version. In the future our methodology can be reused for other algorithms that have a parallel structure.

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