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Field Plate Optimization in Low-Power High-Gain Source-Gated Transistors

Author: Sporea,R.A. · Trainor, M.J. · Young, N.D. · Shannon, J.M. · Silva, S.R.P.
Type:article
Date:2012-02-09
Publisher: IEEE
Institution: Philips Research
Source:IEEE Transactions on Electron Devices, 59 (8), 2012; authors version
Identifier: MS 33.313
Keywords: ltps · polycrystalline silicon tft · polysi tft · source gated transistor · tft
Rights: (c) 2012 IEEE

Abstract

Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high performance analog circuits fabricated in thin-film technologies. The quality of the saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate design can be improved. A simple source field plate around 1μm long situated several tens of nm above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT.

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