Print Email Facebook Twitter Source-Synchronous Interface with All-Digital Data Recovery Title Source-Synchronous Interface with All-Digital Data Recovery: A Low-cost Efficient Design Author Zhang, Shizhao (TU Delft Electrical Engineering, Mathematics and Computer Science; TU Delft Microelectronics) Contributor van Leuken, T.G.R.M. (mentor) Degree granting institution Delft University of Technology Programme Electrical Engineering | Circuits and Systems Date 2017-08-28 Abstract This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed inter-chip communication. The interface is composed of LVDS transceivers as external I/O buffers, and an all-digital data recovery, which can calibrate the received data phase to be aligned to the 90◦ phase of the received half-rate reference clock, for error free data sampling. The proposed data recovery adopts a full-digital scheme, which uses time-to-digital converters (TDC) as phase acquisition, a digitally-controlled delay line (DCDL) to calibrate the phase, and a finite-state machine (FSM) as the control unit. Reference clock generated from phase-locked loops (PLL) or delay-locked loops (DLL) is not needed for the proposed data recovery. The interface is implemented in UMC 65 nm Low-leakage technology, with circuits designed at both transistor-level and RTL-level. The post-layout simulation shows the proposed interface works properly with data rates from 412.4Mbps to 1.25Gbps in all process corners. The total layout area is 688 x 87 µm, and the total power consumption is 16.74 mW. Subject Source-synchronousCDRLVDS To reference this document use: http://resolver.tudelft.nl/uuid:4336470a-041e-452c-b240-39926251d261 Part of collection Student theses Document type master thesis Rights © 2017 Shizhao Zhang Files PDF Thesis_ShizhaoZhang.pdf 6.89 MB Close viewer /islandora/object/uuid%3A4336470a-041e-452c-b240-39926251d261/datastream/OBJ/view