Modeling of Olivocerebellar Neurons using SystemC and High-Level Synthesis

Modeling of Olivocerebellar Neurons using SystemC and High-Level Synthesis

Van Eijk, M.F.

Van Leuken, T.G.R.M. (mentor)
Strydis, C. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics

Circuits and Systems Group

2014-03-04

Neuroscientific experiments often require large amounts of computational power to achieve an efficient research process. Speeding up neuron models, used in such experiments, facilitates faster testing of scientific hypotheses and faster model refinement in order to better replicate biological-cell behavior. To be able to simulate realistic behavior, high-detail neuron models need to be built which require a huge amount of computing power. Hardware acceleration can be used to minimize execution time of such simulations. However, building a hardware implementation is very time-consuming and error-prone. Recent trends in RTL design have resulted in tools which can convert a high-level behavioral hardware description to an RTL description targeting an FPGA, which makes them ideal tools for complex FPGA designs, such as high-detail neuron models. In this thesis, a model of the Inferior-Olivary Nucleus (ION) network has been implemented with synthesizable SystemC and mapped onto an FPGA using a High-Level Synthesis (HLS) tool-flow. A shared-bus architecture has been used to interconnect the various ION-cells in the modeled network. SystemC Transaction Level Modeling (TLM) facilitates fast network-interconnect modeling and verifying of model functionality. We have thus developed a SystemC TLM model that can predict trends of our RTL implementation. With this TLM model, we were able to quickly model large network sizes and assess the model’s scalability with respect to utilized resources and performance. The complete network model has, subsequently, also been synthesized. Xilinx Vivado HLS has been used to convert the SystemC implementation to an RTL description mapped on a Virtex 7 (XC7VX550T) FPGA device. The resulting design achieved a speed-up of 6 compared to a reference C model, making it possible to simulate a network of 48 cells in real-time. Because HLS tools are used, the model can be easily modified to accommodate last-minute changes and models updates by the neuroscientific community.

SystemC
FPGA
HLS
Neuroscience

http://resolver.tudelft.nl/uuid:09167060-4faf-4c31-b894-7d4461eec6cf

2014-03-04

Student theses

master thesis

(c) 2014 Van Eijk, M.F.