A fault tolerant memory architecture for a RISC-V softcore

A fault tolerant memory architecture for a RISC-V softcore

Verhage, A.A.

Van Genderen, A.J. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

CE-MS-2016-16

2016-12-14

Technolution B.V. is developing a custom Reduced Instruction Set Computer (RISC)-V based softcore for implementation on a Field Programmable Gate Array (FPGA). Previously, the softcore used the memory residing on the FPGA only, which is very limited in capacity and limits scaling. To solve this problem, a connection is made from the softcore to the Dynamic RAM (DRAM) interface of the FPGA applied. A cache structure is added to mitigate the performance impact. It makes e?fficient use of the limited, yet fast memory on the FPGA. This thesis report describes the prior art, design considerations, implementation details and results for the realized cache structure and the connection to DRAM. The cache structure is the main topic of this thesis, which has been made as fast and effi?cient as possible, fault tolerant and configurable in capacity. It consists out of a data cache and an instruction cache with slight different parameters. For fault tolerance, both a light and heavy protection scheme are discussed and proposed. Only the light protection scheme is currently implemented and verified. The capacity is configurable as 4, 8, 16 or 32 kB for both types of cache. The connection to DRAM on the other hand makes use of the widely accepted standard of the ARM(TM) Advanced eXtensible Interface (AXI) bus.

FPGA
RISC-V
memory architecture
cache
fault tolerance

http://resolver.tudelft.nl/uuid:0e024a88-8c4f-4213-b1c3-67bfb552c669

Student theses

master thesis

(c) 2016 Verhage, A.A.