Print Email Facebook Twitter Timing and Resource-aware Mapping of Quantum Circuits to Superconducting Processors Title Timing and Resource-aware Mapping of Quantum Circuits to Superconducting Processors Author Lao, L. (TU Delft Computer Engineering; University College London (UCL)) van Someren, J. (TU Delft QCD/Vandersypen Lab) Ashraf, I. (TU Delft QCD/Almudever Lab; TU Delft Computer Engineering; HITEC University) Almudever, Carmen G. (TU Delft QCD/Almudever Lab) Date 2021 Abstract Quantum algorithms need to be compiled to respect the constraints imposed by quantum processors, which is known as the mapping problem. The mapping procedure will result in an increase of the number of gates and of the circuit latency, decreasing the algorithm's success rate. It is crucial to minimize mapping overhead, especially for noisy intermediate-scale quantum (NISQ) processors that have relatively short qubit coherence times and high gate error rates. Most of prior mapping algorithms have only considered constraints, such as the primitive gate set and qubit connectivity, but the actual gate duration and the restrictions imposed by the use of shared classical control electronics have not been taken into account. In this article, we present a mapper called Qmap to make quantum circuits executable on scalable processors with the objective of achieving the shortest circuit latency. In particular, we propose an approach to formulate the classical control restrictions as resource constraints in a conventional list scheduler with polynomial complexity. Furthermore, we implement a routing heuristic to cope with the connectivity limitation. This router finds a set of movement operations that minimally extends circuit latency. To analyze the mapping overhead and evaluate the performance of different mappers, we map 56 quantum benchmarks onto a superconducting processor named Surface-17. Compared to a prior mapping strategy that minimizes the number of operations, Qmap can reduce the latency overhead (LtyOH) up to 47.3% and operation overhead up to 28.6%, respectively. Subject Logic gatesParallel processingProgram processorsQuantum circuitquantum compilationQuantum computingQubitresource-constrained schedulingrouting.Surface treatment To reference this document use: http://resolver.tudelft.nl/uuid:15b99bb8-7f60-4dbd-9e7a-53b86a115802 DOI https://doi.org/10.1109/TCAD.2021.3057583 ISSN 0278-0070 Source IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 41 (2), 359-371 Part of collection Institutional Repository Document type journal article Rights © 2021 L. Lao, J. van Someren, I. Ashraf, Carmen G. Almudever Files PDF 09349092.pdf 576.84 KB Close viewer /islandora/object/uuid:15b99bb8-7f60-4dbd-9e7a-53b86a115802/datastream/OBJ/view