Print Email Facebook Twitter A NMOS Linear Voltage Regulator for Automotive Applications Title A NMOS Linear Voltage Regulator for Automotive Applications Author Li, Y. Contributor Verhoeven, C. (mentor) Hamoen, T. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics & Computer Engineering Programme Microelectronics Date 2012-10-18 Abstract The electronization of automobiles is considered to be a revolution in automotive technology development progress. One trend for automotive electronics design is pursuing higher level integration. System level integrated circuits are needed to simplify the automotive electronics design and increase the reliability of automobiles. In this thesis, a prototype of linear voltage regulator is designed for system level integration. Instead of conventional PMOS linear regulator topology, a NMOS power transistor is chosen as the pass device on considerations of smaller silicon area and better dynamic performance. The characteristic differences of PMOS and NMOS linear regulators are analyzed. Based on the frequency behavior analysis of these two types of regulators, a frequency compensation scheme for the NMOS linear regulator is purposed in this thesis. This purposed scheme is able to accommodate the wide frequency variation of the NMOS linear regulator output pole. The effectiveness of frequency compensation is examined by both mathematical modeling and transistor level simulation. The over-current protection of the NMOS linear regulator is also designed, which is realized by applying another current regulation loop to the voltage regulator. This NMOS linear regulator is able to maintain a constant output current around 250mA in over-current protection scenario. Compared to the existing PMOS linear regulator counterpart, the off-chip ceramic capacitor of this NMOS linear regulator can be reduced to 220nF (10x smaller) without sacrificing the ±2% output voltage accuracy within -40C~175C. The regulator quiescent current at no current load scenario is 12?A. Owing to the introduction of adaptive biasing scheme, the maximum quiescent current is 1.31mA. This adaptive biasing only degrades the current efficiency by maximum 4%. At the end of the thesis, possible maximum load current and external capacitor scaling abilities of this NMOS linear regulator are discussed. Subject NMOSLinear Regulator To reference this document use: http://resolver.tudelft.nl/uuid:1f16f744-5446-4e9b-b9a9-1ff4a947aa33 Embargo date 2012-10-20 Part of collection Student theses Document type master thesis Rights (c) 2012 Li, Y. Files PDF yang_li_thesis_1011_1548.pdf 590.95 KB Close viewer /islandora/object/uuid:1f16f744-5446-4e9b-b9a9-1ff4a947aa33/datastream/OBJ/view