Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

Chen, Y.; Theuwissen, A.J.P.; Chae, Y.

doi:doi:10.1016/j.proeng.2011.12.312

Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

Title

Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

Author

Chen, Y.
Theuwissen, A.J.P.
Chae, Y.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Date

2011-09-04

Abstract

This paper presents a low noise CMOS image sensor (CIS) using 10/12 bit configurable column-parallel single slope ADCs (SS-ADCs) and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with a pinned-photodiode as photon detector. The test sensor was fabricated in a 0.18 colonm CMOS image sensor process from TSMC. The ADC nonlinearity measurement result shows totally 0.58% nonlinearity. Using the proposed column-parallel SS-ADC with digital CMS technique, 65% random noise reduction is obtained. The significant noise reduction enhances the sensor's SNR with 9 dB.

Subject

CMOS image sensor
column-parallel ADC
digital correlated multiple sampling

To reference this document use:

http://resolver.tudelft.nl/uuid:217752ff-9b7a-43df-ad6c-fb4f5bc11342

DOI

https://doi.org/10.1016/j.proeng.2011.12.312

Publisher

Elsevier

ISSN

1877-7058

Source

Procedia Engineering, 25, 2011