Spiderweb Array

Spiderweb Array: A Sparse Spin-Qubit Array

Boter, J.M. (TU Delft QuTech Advanced Research Centre; TU Delft QCD/Vandersypen Lab; Kavli institute of nanoscience Delft)
Dehollain Lorenzana, J.P. (TU Delft QCD/Vandersypen Lab; TU Delft QuTech Advanced Research Centre; Kavli institute of nanoscience Delft; University of Technology Sydney)
van Dijk, J.P.G. (TU Delft Quantum Circuit Architectures and Technology; TU Delft QuTech Advanced Research Centre; Kavli institute of nanoscience Delft)
Xu, Yuanxing (Kavli institute of nanoscience Delft; Student TU Delft)
Hensgens, T. (TU Delft QCD/Vandersypen Lab; TU Delft QuTech Advanced Research Centre; Kavli institute of nanoscience Delft)
Versluis, R. (TU Delft BUS/TNO STAFF; TU Delft QuTech Advanced Research Centre; TNO)
Naus, H.W.L. (TU Delft BUS/TNO STAFF; TU Delft QuTech Advanced Research Centre; TNO)
Veldhorst, M. (TU Delft QN/Veldhorst Lab; TU Delft QuTech Advanced Research Centre; Kavli institute of nanoscience Delft)
Sebastiano, F. (TU Delft Quantum Circuit Architectures and Technology; TU Delft QuTech Advanced Research Centre; TU Delft Quantum & Computer Engineering)
Vandersypen, L.M.K. (TU Delft QuTech Advanced Research Centre; TU Delft QN/Vandersypen Lab; Kavli institute of nanoscience Delft; Intel Labs)

Quantum & Computer Engineering

2022

One of the main bottlenecks in the pursuit of a large-scale-chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional array with about 12μm pitch, we create space to implement locally integrated sample-and-hold circuits. This allows us to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling, leading to a Rent's exponent as low as p=0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit array. This work presents a complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and identifying remaining challenges for achieving full fault-tolerant quantum computation. It thereby significantly closes the gap towards a fully CMOS-compatible quantum computer implementation.

http://resolver.tudelft.nl/uuid:336917ed-f8f0-4a79-93b7-978d2bab803e

https://doi.org/10.1103/PhysRevApplied.18.024053

2331-7019

Physical Review Applied, 18 (2)

Institutional Repository

journal article

© 2022 J.M. Boter, J.P. Dehollain Lorenzana, J.P.G. van Dijk, Yuanxing Xu, T. Hensgens, R. Versluis, H.W.L. Naus, M. Veldhorst, F. Sebastiano, L.M.K. Vandersypen