A Low-Noise Fractional-N Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

A Low-Noise Fractional-N Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Zong, Z. (TU Delft Electronics)
Chen, Peng (University College Dublin)
Staszewski, R.B. (TU Delft Electronics; University College Dublin)

2019

In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f ³ ) and thermal (1/f ² ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to 1/f ³ PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213-277-fs rms jitter in the 57.5-67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300-400 kHz.

60 GHz
All-digital phase-locked loop (ADPLL)
Digital-to-time converter (DTC)
Digitally controlled oscillator (DCO)
Flicker noise
Flicker noise upconversion
Fractional spur suppression
Fractional-N PLL
Harmonic boosting
Harmonic extraction
Implicit multiplier
Mm-wave (mmW)
Phase noise (PN)
Time-to-digital converter (TDC)

http://resolver.tudelft.nl/uuid:556432e9-11a7-47f2-9019-18e7ccc9f1fd

https://doi.org/10.1109/JSSC.2018.2883397

0018-9200

IEEE Journal of Solid State Circuits, 54 (3), 755-767

Institutional Repository

journal article

© 2019 Z. Zong, Peng Chen, R.B. Staszewski