An Intermediate Representation for Composable Typed Streaming Dataflow Designs

An Intermediate Representation for Composable Typed Streaming Dataflow Designs

Reukers, Matthijs A. (Student TU Delft)
Tian, Y. (TU Delft Computer Engineering)
Al-Ars, Z. (TU Delft Computer Engineering)
Hofstee, H.P. (TU Delft Computer Engineering; IBM Austin)
Brobbel, M. (TU Delft Computer Engineering; Voltron Data Inc.)
Peltenburg, J.W. (TU Delft Computer Engineering; Voltron Data Inc.)
van Straten, J. (TU Delft BUS/Quantum Delft; Voltron Data Inc.)

2023

Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. These data types are extensively used in a many application domains, such as big data and SQL applications. This way, Tydi provides a higher-level method for defining interfaces between components as opposed to existing bit- and byte-based interface specifications. In this paper, we introduce an open-source intermediate representation (IR) which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi's streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system. The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior. To demonstrate this IR, we have created a grammar, parser, and query system, and paired these with a backend targeting VHDL.

data structures
hardware description languages
hardware streams
intermediate representations
open source software

http://resolver.tudelft.nl/uuid:5d63ead9-5cd3-4a13-8ba7-a99c1e7fbff8

1613-0073

CEUR Workshop Proceedings, 3462

Joint Workshops at the 49th International Conference on Very Large Data Bases, VLDBW 2023, 2023-08-28 → 2023-09-01, Vancouver, Canada

Institutional Repository

journal article

© 2023 Matthijs A. Reukers, Y. Tian, Z. Al-Ars, H.P. Hofstee, M. Brobbel, J.W. Peltenburg, J. van Straten