A highly linear downconverter for on-chip linearization of digital power amplifiers

A highly linear downconverter for on-chip linearization of digital power amplifiers

Hardeman, Gilbert (TU Delft Electrical Engineering, Mathematics and Computer Science)

de Vreede, L.C.N. (mentor)
Mul, D.P.N. (mentor)

Delft University of Technology

Electrical Engineering

2021-11-29

This work presents a highly linear quadrature down-converter topology intended for the linearization of digital Transmitters(DTX). By integrating it with a DTX, a fully integrated on-chip output-signal correction loop comes closer to its realization. The proposed down conversion architecture can measure the errors introduced by the non-linearity of the transmitter, rather than the transmitter output itself. These errors are determined by comparing the downconverted transmitter output signals with its analog ideal baseband I and Q reference signals. The reference signals are provided by low-power digital-to-analog converters(DACs), using the same IQ data input as the power DTX. This approach reduces the resolution/dynamic range requirements on the trans-impedance-amplifier (TIA) and analog-to-digital converters(ADCs) since the error signals have a reduced dynamic range compared to the transmitter’s output signal itself. These lower requirements on the ADCs and elimination of off-chip couplers and filter sease the integration of a complete digital pre-distortion (DPD) correction loop in future DTX implementations. As the core of this thesis work, a linear harmonic rejection mixer was designed. It uses resistors inits mixer branches to implement the proper currenct scaling needed for harmonic rejection (HR). The resulting HR mixer avoids the unwanted down-conversion of the higher harmonics of the DTX to the base band frequencies of interest. Also, atrans-impedance amplifier was designed with the proposed passive mixer. These TIAs are based on an inverter topology for maximum tranconductance and were biased for optimal linearity and offered a bandwidth over 1.8GHz. The proposed DTX error-detection architectureis implemented in the current domain. Performing the subtraction before the TIA drastically reduces the voltage swing at the input of the TIA, benefiting the linearity of the mixer and reference DAC. The overall HR-mixer configuration is simulated for its linearity, yielding an IIP3 of 49dBm, which to the best of the author’s knowledge, is the best-reported linearity for high bandwidth down-converting applications.

http://resolver.tudelft.nl/uuid:806bbe8d-e306-42c7-a030-8c300bd4910c

2023-11-29

Student theses

master thesis

© 2021 Gilbert Hardeman