Charge Domain Interlacing CMOS Image Sensor Design

Charge Domain Interlacing CMOS Image Sensor Design

Xu, Y.

Theuwissen, A. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

2009-08-31

This thesis presents a CMOS image sensor which can implement the charge domain interlacing principle. Inspired by the shared amplifier pixel structure and based on a pinned photodiode four transistor (4T) structure, two innovative pixel designs combined with two different readout directions are presented. These novel pixels are designed to fit the charge domain interlacing principle, which used the charge binning technology in the field integration mode of interlaced scan to improve the signal-to-noise ratio of the sensor. To realize this working principle and compared it with other working modes, a programmable universal image sensor peripheral circuit is designed for controlling and driving the pixel array in the most flexible and most efficient way. As a result, the designed sensor can be used not only in the progressive scan mode, frame integration interlaced scan, and voltage domain interlacing mode but also in the charge domain interlacing mode. This is a very unique feature for CMOS image sensors, and without the shared pixel concept, charge domain interlacing was only possible with CCDs. The proposed image sensor is implemented in TSMC 0.18um 1P6M CMOS technology. Some preliminary measurement results of the chip are shown to prove the functional correctness of the image sensor.

CMOS image sensor
charge binnning
interlaced scan

http://resolver.tudelft.nl/uuid:80ea30e9-11c3-4e7e-b250-7de6015f4744

2009-09-02

Student theses

master thesis

(c) 2009 Xu, Y.