A low noise, low power dynamic amplifier with common mode detect and a low power, low noise comparator for pipelined SAR-ADC

A low noise, low power dynamic amplifier with common mode detect and a low power, low noise comparator for pipelined SAR-ADC

Astgimath, S.P.

Long, J.R. (mentor)
Bult, K. (mentor)
Van der Goes, F.M.L. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

2012-08-30

This thesis presents a high gain, low noise and low power dynamic residue amplifier and a low power, low noise dynamic comparator designed in TSMC 28nm process for a two step Pipelined SAR-ADC. The cascoded integrator dynamic residue amplifier (CIDRA) achieves a gain of 30dB with THD of 47dB (11 mV pp input). The input referred noise across tem- perature and process corner is 55 µV and it operates at a frequency of 500MHz while the energy consumption is 390 fJ. The low power and low noise pseudo-latch preamp dynamic comparator (PLPDC) shows a delay of 250pSec for a differential input of 16 pV and consumes 91 fJ (current is 91 µA for 100 MHz clock) of energy. The input referred offset is 4 mV (?).

dynamic amplifier
dynamic comparator
pipelined SAR-ADC
noise analysis

http://resolver.tudelft.nl/uuid:92f240dd-67ec-4f61-9210-4763d7b8a90a

Student theses

master thesis

(c) 2012 Astgimath, S.P.