Print Email Facebook Twitter A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS Title A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS Author Chen, Peng (University College Dublin) Zhang, Feifei (University College Dublin) Zong, Z. (TU Delft Electronics; NXP Semiconductors) Hu, Suoping (University College Dublin) Siriburanon, Teerachot (University College Dublin) Staszewski, R.B. (University College Dublin) Date 2019-11-01 Abstract This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold comparator. The DTC operation mechanism is analyzed and design tradeoffs are investigated. The proposed DTC consumes merely 31 μW from a 1-V supply when clocked at 40 MHz, while achieving a fine resolution of 148 fs over a 9-bit range. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.96/1.07 LSB. Subject Capacitor-based digital-to-analog converter (C-DAC)constant slopedigital-to-time converter (DTC)femtosecond resolutionintegral nonlinearity (INL)phase-locked loop (PLL)power-efficientultra-low power (ULP) To reference this document use: http://resolver.tudelft.nl/uuid:abb92aa0-b726-4991-9078-324d9725a972 DOI https://doi.org/10.1109/JSSC.2019.2939663 ISSN 0018-9200 Source IEEE Journal of Solid State Circuits, 54 (11), 3075-3085 Part of collection Institutional Repository Document type journal article Rights © 2019 Peng Chen, Feifei Zhang, Z. Zong, Suoping Hu, Teerachot Siriburanon, R.B. Staszewski Files PDF 08850049.pdf 4.21 MB Close viewer /islandora/object/uuid:abb92aa0-b726-4991-9078-324d9725a972/datastream/OBJ/view