Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Annink, Edian B. (University of Twente)
Rauwerda, Gerard (Recore Systems B.V.)
Hakkennes, Edwin (Recore Systems B.V.)
Menicucci, A. (TU Delft Space Systems Egineering)
Di Mascio, S. (TU Delft Space Systems Egineering; European Space Agency (ESA))
Furano, Gianluca (European Space Agency (ESA))
Ottavi, Marco (University of Twente; University of Rome Tor Vergata)

Cassano, Luca (editor)
Chakravarty, Sreejit (editor)
Bosio, Alberto (editor)

2022

Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.

Bloom Filters
Hardware Dependability
Hardware Security
Hardware Trojans
RISC-V

http://resolver.tudelft.nl/uuid:c912cc55-2347-43ed-8637-31fd0a7fef66

https://doi.org/10.1109/DFT56152.2022.9962340

Institute of Electrical and Electronics Engineers (IEEE)

2023-07-01

9781665459389

Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022

35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, 2022-10-19 → 2022-10-21, Austin, United States

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, 2576-1501, 2022-October

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Institutional Repository

conference paper

© 2022 Edian B. Annink, Gerard Rauwerda, Edwin Hakkennes, A. Menicucci, S. Di Mascio, Gianluca Furano, Marco Ottavi