A DfT architecture for 3D-SICs based on a standardizable die wrapper

Marinissen, E.J.; Chi, C.C.; Konijnenburg, M.; Verbree, J.

doi:doi:10.1007/s10836-011-5269-9

A DfT architecture for 3D-SICs based on a standardizable die wrapper

Title

A DfT architecture for 3D-SICs based on a standardizable die wrapper

Author

Marinissen, E.J.
Chi, C.C.
Konijnenburg, M.
Verbree, J.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Computer Engineering

Date

2011-12-31

Abstract

Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1149.1 or IEEE Std 1500. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies

Subject

3D stacked ICs · through-silicon via · manufacturing test · design-for-test · wrapper · test access mechanism · standardization · IEEE 1149.1 · IEEE 1500

To reference this document use:

http://resolver.tudelft.nl/uuid:eeeb8983-b927-4e82-b727-7ec31e16e2c1

DOI

https://doi.org/10.1007/s10836-011-5269-9

Publisher

Springer

ISSN

0923-8174

Source

http://www.springerlink.com/content/w1256707881x3443/