Print Email Facebook Twitter A 10 Gbps Wireline Transceiver Link Title A 10 Gbps Wireline Transceiver Link: To Interface Future RF-DACs Author Feng, Jun (TU Delft Electrical Engineering, Mathematics and Computer Science) Contributor de Vreede, L.C.N. (mentor) Alavi, S.M. (mentor) Cavallo, D. (graduation committee) Degree granting institution Delft University of Technology Date 2020-08-21 Abstract This thesis presents the development of circuits and systems for fast wireline transceiver links that will enable a move towards highly integrable RF digital-to-analog converters. A new perspective on the analysis of bit error rates in wireline links leads to the PAM spectral design space chart: a novel, visual system design analysis tool for PAM wireline circuit designers. Moreover, a <2 mW/Gbps/lane, 10 Gbps wireline transmitter has been designed and taped-out in 40 nm CMOS. The proposed inherently pipelined 16:1 multiplexer and current mode logic driver design procedure are the key enablers for this performance. Finally, for development of a 10 Gbps wireline receiver, a novel self-synchronized receiver design is proposed that removes the need of a classical clock and data recovery loop. At its core, this receiver comprises the design of a high-speed two-tail comparator and an asynchronous metastability detection loop. Subject WirelineTransmitterReceiverPAMTransceiverSerDes To reference this document use: http://resolver.tudelft.nl/uuid:f121cb32-1b27-4b1d-bfd0-89410d70ccd1 Embargo date 2022-08-31 Part of collection Student theses Document type master thesis Rights © 2020 Jun Feng Files PDF JunFeng_ThesisReport.pdf 10.29 MB Close viewer /islandora/object/uuid:f121cb32-1b27-4b1d-bfd0-89410d70ccd1/datastream/OBJ/view