Print Email Facebook Twitter 4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter Title 4 Bits 250MHz Sampling Rate CMOS Pipelined Analog-to-Digital Converter Author Wang, J. Contributor Serdijn, W. (mentor) Lotfi, R. (mentor) Serdijn, W. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Circuit Design Date 2009-05-15 Abstract a 4-bit 250MHz sampling rate pipelined A/D converter, with 1.5-bit resolution per stage, has been designed by Cadence using TSMC 0.13um CMOS process. The ADC which works at 1.2 V supply voltage dissipates 15.23 mW and has an ENOB of 3.7 bits @ 100MHz sampling condition. The maximum DNL is 0.38 LSB, and the maximum INL is 0.352 LSB Subject Pipeline ADC To reference this document use: http://resolver.tudelft.nl/uuid:119e4ef6-cc88-4f47-a84d-882bb9e0d691 Part of collection Student theses Document type master thesis Rights (c) 2009 Wang, J. Files PDF fianl_thesis.pdf 514.9 KB Close viewer /islandora/object/uuid:119e4ef6-cc88-4f47-a84d-882bb9e0d691/datastream/OBJ/view