Print Email Facebook Twitter Sensitivity Modeling of On-chip Capacitances: Parasitics Extraction for Manufacturing Variability Title Sensitivity Modeling of On-chip Capacitances: Parasitics Extraction for Manufacturing Variability Author Bi, Y. Contributor Dewilde, P.M. (promotor) Van der Meijs, N.P. (promotor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics & Computer Engineering Date 2012-07-06 Abstract With each new generation of IC process technologies, the impact of manufacturing variability is increasing. As such, design optimality is harder and harder to achieve and effective modeling tools and methods are needed to capture the effects of variability in such a way that it is understandable and useful to IC designers. Our research has been stimulated by such needs and the goal of our work is to study and model the effect of manufacturing variations (systematic and random) on on-chip interconnects, and to make it transparent to designers. Specifically, we focus on interconnect capacitances. We propose a sensitivity-based modeling method and present a fast algorithm for sensitivity computation. The algorithm is applicable for layout parasitics extraction (LPE) tools based on a boundary element method (BEM). It is efficient in the sense that both the nominal values of capacitances and their sensitivities with respect to multiple parameters can be obtained with only one system solve. Such an algorithm forms a core of other algorithms for handling various aspects of variability-related problems in practice. Two extension algorithms have been developed in this thesis. The first extension provides a technique for computing the statistical properties of interconnect capacitances resulting from line-edge-roughness (LER). Using the proposed algorithm, the nominal values of capacitances as well as their statistical properties accounting for both the systematic and the random variations can be obtained at a negligible extra computational time, compared to the nominal capacitance computation. The fast estimate of LER effects on interconnect capacitances can be very useful for designs of passive components with high-precision requirements. In this context, a real design case is studied. Supported by the measurement results on test chips, our technique successfully estimates the mismatch of capacitances due to LER. Calculating the statistical properties of capacitances is, in many cases, not the eventual purpose of modeling manufacturing variabilities. Instead, it is the circuit performance, e.g. the system response, that designers care about. Traditionally, the statistical properties of the system response are obtained by the Monte-Carlo approach, which, however, suffers from a huge computational burden due to the need of sampling the parameter space. This problem can be solved by the second extension algorithm, which achieves zero parameter sampling, by combining the proposed sensitivity-based parameterized parasitics extraction technique and a structure-preserving parameterized model order reduction technique. It demonstrates a highly efficient methodology to obtain the statistical properties, such as the mean and the standard deviation, of the system response of RC nets subject to systematic variations. The proposed algorithm for the sensitivity computation has been implemented in a layout-to-circuit parasitics extractor SPACE. Subject variabilitycapacitancessensitivityinterconnectmodeling To reference this document use: http://resolver.tudelft.nl/uuid:4889f2c0-318b-45ff-b5d4-40682407938d ISBN 9789461860392 Part of collection Institutional Repository Document type doctoral thesis Rights (c) 2012 Bi, Y. Files PDF thesis-Bi-final.pdf 11.58 MB Close viewer /islandora/object/uuid:4889f2c0-318b-45ff-b5d4-40682407938d/datastream/OBJ/view