Print Email Facebook Twitter A hierarchical layout to circuit extractor using a finite state approach Title A hierarchical layout to circuit extractor using a finite state approach Author Annevelink, J. Dewilde, P. Fokkema, J.T. Date 1983 Subject circuit-layout-CAD large-scale-integration LSI- hierarchical-layout-to-circuit-extractor hierarchical-description finite-state-scanning-algorithm symbolic-description electrical-circuit switch-level-description NMOS-circuits To reference this document use: http://resolver.tudelft.nl/uuid:6db2756c-1ca8-422c-9ecf-5c1e6a822b45 Publisher IEEE Comput. Soc. Press, Silver Spring, MD, USA Source Proceedings-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-ICCD-'83.1983: USA Conference-Paper IEEE, 481-484. (1983) Part of collection Institutional Repository Document type conference paper Files PDF 878021.pdf 279.49 KB Close viewer /islandora/object/uuid:6db2756c-1ca8-422c-9ecf-5c1e6a822b45/datastream/OBJ/view