Characterization of waferstepper and process related front- to backwafer overlay errors in bulk micro machining using electrical overlay test structures

Characterization of waferstepper and process related front- to backwafer overlay errors in bulk micro machining using electrical overlay test structures

Van Zeijl, H.W.
Bijnen, F.G.C.
Slabbekoorn, J.

Electrical Engineering, Mathematics and Computer Science

Delft Institute of Microelectronics and Submicron Technologies

2004-08-16

To validate the Front- To Backwafer Alignment (FTBA) calibration and to investigate process related overlay errors, electrical overlay test structures are used that requires FTBA [1]. Anisotropic KOH etch through the wafer is applied to transfer the backwafer pattern to the frontwafer. Consequently, the crystal orientation introduces an overlay shift. A double exposure method is presented to separate the process-induced shift from the FTBA shift. The process induced overlay shift can run up to 3µm, large compared to the expected FTBA error (around 0.1 µm). The measured overlay distribution is 0.45 µm (3 ?) this includes both waferstepper and process related overlay errors. The overlay distribution, corrected for waferstepper related overlay errors, like lens distortion, resembles the overlay distribution of the bulk micromachining (BMM) process; 0.26µm (3?). The procedures described in this work provide a quantitative method of describing the waferstepper and process related front to backwafer overlay errors.

bulk micro machining KOH etching
front to backwater alignment
electrical overlay measurements

http://resolver.tudelft.nl/uuid:911c8b6f-fdbf-4211-a305-27c0fd139cc6

SPIE

0277-786X

Proceedings of SPIE, 2004 vol. 5455

Institutional Repository

conference paper

(c)2004 Van Zeijl, H.W., Bijnen, F.G.C., Slabbekoorn, J.