Print Email Facebook Twitter Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging Title Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging Author Hou, F. (TU Delft Electronic Components, Technology and Materials; National Center for Advanced Packaging; Chinese Academy of Sciences) Wang, Qidong (Chinese Academy of Sciences) Chen, Min (Zhejiang University; Chinese Academy of Sciences) Zhang, Kouchi (TU Delft Electronic Components, Technology and Materials) Ferreira, Jan Abraham (University of Twente) Wang, Wenbo (Shenzhen Institute of Wide-bandgap Semiconductors) Ma, R. (National Center for Advanced Packaging; Chinese Academy of Sciences) Su, Meiying (Chinese Academy of Sciences; National Center for Advanced Packaging) Song, Yang (National Center for Advanced Packaging; Chinese Academy of Sciences) Date 2020-03-01 Abstract In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermo-mechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances. Subject Electro-thermo-mechanical codesignphase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power moduleprinted circuit board (PCB)-embedded packagestatic characterizationswitching characterization To reference this document use: http://resolver.tudelft.nl/uuid:966eda00-d1ce-47e8-84d7-6604ed7cb714 DOI https://doi.org/10.1109/JESTPE.2019.2952238 ISSN 2168-6777 Source IEEE Journal of Emerging and Selected Topics in Power Electronics, 8 (1), 367-380 Part of collection Institutional Repository Document type journal article Rights © 2020 F. Hou, Qidong Wang, Min Chen, Kouchi Zhang, Jan Abraham Ferreira, Wenbo Wang, R. Ma, Meiying Su, Yang Song, More Authors Files PDF 08894039.pdf 7 MB Close viewer /islandora/object/uuid:966eda00-d1ce-47e8-84d7-6604ed7cb714/datastream/OBJ/view