Is RISC-V ready for Space? A Security Perspective

Is RISC-V ready for Space? A Security Perspective

Cassano, Luca (Politecnico di Milano)
Di Mascio, S. (TU Delft Space Systems Egineering)
Palumbo, Alessandro (University of Rome Tor Vergata)
Menicucci, A. (TU Delft Space Systems Egineering)
Furano, Gianluca (European Space Agency (ESA))
Bianchi, Giuseppe (University of Rome Tor Vergata)
Ottavi, Marco (University of Rome Tor Vergata; University of Twente)

Cassano, Luca (editor)
Chakravarty, Sreejit (editor)
Bosio, Alberto (editor)

2022

Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.

Hardware Security
Hardware Trojan Horses
Microarchitectural Side-Channel Attacks
Microprocessors
RISC-V
Space Applications.

http://resolver.tudelft.nl/uuid:b071b6f0-7888-4f74-ac56-9864f457886f

https://doi.org/10.1109/DFT56152.2022.9962352

Institute of Electrical and Electronics Engineers (IEEE)

2023-07-01

9781665459389

Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022

35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, 2022-10-19 → 2022-10-21, Austin, United States

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, 2576-1501, 2022-October

Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Institutional Repository

conference paper

© 2022 Luca Cassano, S. Di Mascio, Alessandro Palumbo, A. Menicucci, Gianluca Furano, Giuseppe Bianchi, Marco Ottavi