Microelectronic design of a pseudo voltage clamp for a 0.18um CMOS-based mesoscale neural interface for intracellular in-vitro recording and stimulation

Microelectronic design of a pseudo voltage clamp for a 0.18um CMOS-based mesoscale neural interface for intracellular in-vitro recording and stimulation

del Rivero Cortázar, Aitor (TU Delft Electrical Engineering, Mathematics and Computer Science)

Ulusan, H. (mentor)
Cardes, F. (mentor)
Montagne, A.J.M. (mentor)
Lopes Marta da Costa, T.M. (graduation committee)
Verhoeven, C.J.M. (graduation committee)
Serdijn, W.A. (graduation committee)

Delft University of Technology

Electrical Engineering | Microelectronics

2021-08-30

The need to understand how the brain works has sparked interest in electrode arrays to record neural signals. Intracellular recordings with nanoelectrodes that penetrate the cell allow better signal quality and additional functions such as voltage clamping to set the neuron's transmembrane voltage. The voltage clamp aims to facilitate the independent study of the ionic channel contributions to the overall neuron's transmembrane current for applications such as drug screening. This thesis aims to design a voltage clamp with CMOS technology to integrate into an intracellular neural interface system. The circuit, a trans-impedance amplifier, needs to be low-noise, small, and have wide clamping and output voltage ranges. The amplifier's design follows a structured methodology and uses symbolic analysis with the software SLiCAP and simplified EKV models aiming for easier readjustments and transparency for other researchers. The controller is an Operational Amplifier with a differential pair input-stage, an unbalanced common-source output-stage, and frequency compensation. The feedback network is a pseudo-resistor due to the enormous gains required to record the currents in the electrode of about 100 pA - 1 nA. The final simulations estimate a trans-impedance gain from the electrode to the load range of [2 M,1 G] V/A, a clamping voltage range of [0.90, 3.16] V, an output voltage range of [0.50, 3.16] V, and an output-referred noise between 0.095 and 0.41 mV_rms depending on the gain. The power usage is 49.1 uW/pixel and the area 0.0092 mm²/pixel. Post-layout simulations show stability degradation due to the influence of parasitics in the pseudo-resistor.

Analog integrated circuits
Application specific integrated circuits
Biomedical electronics
CMOS integrated circuits
Design automation
Design methodology
Electrophysiology
In vitro
Intracellular recordings
Microelectrode arrays
MOS devices
Nanobiointerfaces
Nanoelectrode arrays
Neural interface
Neurons
Voltage clamps

http://resolver.tudelft.nl/uuid:c6fd0fb6-20f7-43ee-bf7e-261b293fa00f

Student theses

master thesis

© 2021 Aitor del Rivero Cortázar