Print Email Facebook Twitter A Sampled Voltage Reference Title A Sampled Voltage Reference Author Rooijers, C.T. Contributor Makinwa, K.A.A. (mentor) Huijsing, J.H. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics Programme Electronic Instrumentation Date 2016-01-25 Abstract A sampled voltage reference aims to achieve both low-power and low-noise by storing the output of a voltage reference on a capacitor for a long time. This allows the reference to be switched off during the hold period, which leads to lower average power. At the same time, all the voltage reference's noise is pushed down into a bandwidth determined by the refresh frequency, while the buffer can be made low-noise by auto-zeroing. The design of a continuous-time auto-zeroed buffer with low-noise and low-offset is presented. Various techniques have been used to reduce the transients created by auto-zeroing. In simulation the transients are below 1 µV peak-to-peak, but the effectiveness of the techniques could not be evaluated in measurements. The design of a low leakage sample and hold circuit is also presented. This uses bootstrap techniques to maintain zero potential across critical parasitic diodes. It is shown to be effective, resulting in a drift of about 5 µV per second. A mechanism is found which explains how the buffer's residual offset is transferred to the hold capacitor. A special slow-chopping technique is presented and implemented to try to reverse the leakage due to this residual offset. The final implemented design suffers from a large coupling between the high frequency reference clock and the output. It is shown that this causes a much higher residual offset than expected, which in turn increases the leakage of the hold capacitor. With a measured residual offset in the order of several 100 µVs and an auto-zeroing frequency of 2 kHz, the leakage in 1 s is 34 mV. Via simulation it is shown that with a lower residual offset, the leakage can be greatly reduced. Methods of improving the current design have been investigated. A new clocking scheme is proposed and simulated. Improvements to the buffer are also proposed, which should lower its 1/f noise corner. This would allow for a lower auto-zeroing frequency, which in turn will further reduce the leakage. Subject Sampled Voltage ReferenceDuty-cyclingLow powerLow noiseLow leakageSample-and-holdLow Switching transientsContinuous-time auto-zeroed bufferLow offsetCharge kickbackSlow-choppingDead time To reference this document use: uuid:ce632c5c-ea10-4aa5-a7bf-2b4a24bc78b4 Embargo date 2021-01-01 Part of collection Student theses Document type master thesis Rights (c) 2016 Rooijers, C.T.