Print Email Facebook Twitter VHDL to SystemC: The Design of a Translator Title VHDL to SystemC: The Design of a Translator Author Schoneveld, G.J. Contributor Van Leuken, T.G.R.M. (mentor) Van der Veen, A.J. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics & Computer Engineering Date 2009-08-27 Abstract VHDL and SystemC are both languages to describe or model circuits and systems. Reasons could exist for wanting to translate a model in VHDL to an equivalent model in SystemC. A system in SystemC can be needed for modeling a system with a software part, for a faster simulation, or because some tools only support SystemC. This thesis presents a tool that performs this translation from VHDL to SystemC. The tool is constructed like a regular compiler: It consists of a front-end that reads and analyzes VHDL code and a back-end that generates SystemC code. The front-end came from the FreeHDL project and we have made the back-end ourselves. The back-end generates SystemC code by traversing the tree that comes from the front-end. We have validated that the tool is suitable for simulation purposes and we have verified that the tool translates VHDL without problems in most cases we have seen in the wild. Subject VHDLSystemCtranslatorconvertercompiler To reference this document use: http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968 Part of collection Student theses Document type master thesis Rights (c) 2009 Schoneveld, G.J. Files PDF thesis.pdf 411.01 KB Close viewer /islandora/object/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968/datastream/OBJ/view