A 0.7-V 0.43-pJ/cycle Wakeup Timer based on a Bang-bang Digital-Intensive frequency-Locked-Loop for IoT Applications

A 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. A self-biased ΣΔ digitally controlled oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the...

A Digital-Intensive Wakeup Timer based on an RC Frequency-Locked Loop for Internet-of-Things Applications

This thesis presents an ultra-low power wakeup timer locked to an RC time constant that can meet the stringent power requirements of the nodes for Internet-of-Things (IoT) applications. The wakeup timer, fabricated in a 40-nm CMOS process, employs a bang-bang digital-intensive frequency-locked loop (DFLL). A self-biased ΣΔ digitally controlled...