Source-Synchronous Interface with All-Digital Data Recovery: A Low-cost Efficient Design

This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed inter-chip communication. The interface is composed of LVDS transceivers as external I/O buffers, and an all-digital data recovery, which can calibrate the received data phase to be aligned to the 90^◦ phase of the received half-rate reference...