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Gao, Z. (author), He, J. (author), Fritz, Martin (author), Shen, Y. (author), Zong, Z. (author), Spalink, Gerd (author), Alavi, S.M. (author), Staszewski, R.B. (author), Babaie, M. (author)This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO)...journal article 2023
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Gao, Z. (author), Fritz, Martin (author), Spalink, Gerd (author), Staszewski, R.B. (author), Babaie, M. (author)In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce a new non-uniform clock compensation (NUCC) scheme to tackle an EVM degradation resulting from the beneficial use of a time-varying sampling clock that is re-timed to the phase-modulated...journal article 2023
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Anders, Jens (author), Babaie, M. (author), Bashir, Imran (author), Charbon, Edoardo (author), Geck, Lotte (author), Ibrahim, Mohamed I. (author), Sebastiano, F. (author), Staszewski, R.B. (author), Vladimirescu, A. (author)Over the past decade, significant progress in quantum technologies has been made, and hence, engineering of these systems has become an important research area. Many researchers have become interested in studying ways in which classical integrated circuits can be used to complement quantum mechanical systems, enabling more compact, performant...journal article 2023
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Alarcon, Eduard (author), Abadal, Sergi (author), Sebastiano, F. (author), Babaie, M. (author), Charbon-Iwasaki-Charbon, E. (author), Bolivar, Peter Haring (author), Palesi, Maurizio (author), Staszewski, R.B. (author), Almudever, Carmen G. (author)The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via...conference paper 2023
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Chen, Y. (author), Gong, J. (author), Staszewski, R.B. (author), Babaie, M. (author)In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the...journal article 2022
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Gao, Z. (author), Fritz, Martin (author), He, J. (author), Spalink, Gerd (author), Staszewski, R.B. (author), Alavi, S.M. (author), Babaie, M. (author)We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre...conference paper 2022
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Gao, Z. (author), He, J. (author), Fritz, Martin (author), Gong, J. (author), Shen, Y. (author), Zong, Z. (author), Chen, Peng (author), Staszewski, R.B. (author), Alavi, S.M. (author), Babaie, M. (author)In a fractional-N PLL, it is beneficial to minimize the input range of its phase detector (PD) as it promotes better linearity and higher PD gain for suppressing noise contributions of the following loop components. This can be done by canceling the predicted instantaneous time offset between the frequency reference (FREF) and the variable...conference paper 2022
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Li, Chao Chieh (author), Yuan, Min Shueh (author), Liao, Chia Chun (author), Chang, Chih Hsien (author), Lin, Yu Tso (author), Tsai, Tsung Hsien (author), Huang, Tien Chien (author), Liao, Hsien Yuan (author), Staszewski, R.B. (author)In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched...journal article 2021
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Urso, A. (author), Chen, Y. (author), Staszewski, R.B. (author), Dijkhuis, Johan F. (author), Stanzione, Stefano (author), Liu, Y. (author), Serdijn, W.A. (author), Babaie, M. (author)In this paper, we propose a new scheme to directly power a 4.9-5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage...journal article 2020
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Chen, Peng (author), Zhang, Feifei (author), Zong, Z. (author), Hu, Suoping (author), Siriburanon, Teerachot (author), Staszewski, R.B. (author)This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold...journal article 2019
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Kuo, Feng Wei (author), Zong, Z. (author), Chen, Huan Neng Ron (author), Cho, Lan Chou (author), Jou, Chewn Pu (author), Chen, Mark (author), Staszewski, R.B. (author)This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range,fine-resolution DCO with only switchable metal capacitors. A third-harmonic boosting DCO simultaneously generates 22.5-28 GHz and sufficiently strong 68-84 GHz...conference paper 2019
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Gao, Z. (author), Hu, Yizhe (author), Siriburanon, Teerachot (author), Staszewski, R.B. (author)This paper proposes a mm-wave quadrature frequency generator using injection-locked harmonic extractors (HEs) incorporated with quadrature class-F oscillators. While maintaining high output levels at 28 GHz, the utilization of injection locking technique improves the effective quality ($Q$)-factor and helps to achieve a fundamental harmonic...conference paper 2019
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A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and CancellationChen, Y. (author), Liu, Yao-Hong (author), Zong, Z. (author), Dijkhuis, Johan (author), Dolmans, Guido (author), Staszewski, R.B. (author), Babaie, M. (author)In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail...journal article 2019
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Zong, Z. (author), Chen, Peng (author), Staszewski, R.B. (author)In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f <sup>3</sup> ) and thermal (1/f <sup>2</sup> ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong...journal article 2019
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Pourmousavian, Naser (author), Kuo, Feng Wei (author), Siriburanon, Teerachot (author), Babaie, M. (author), Staszewski, R.B. (author)This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to...journal article 2018
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Patra, B (author), Incandela, R.M. (author), van Dijk, J.P.G. (author), Homulle, Harald (author), Song, Lin (author), Shahmohammadi, M. (author), Staszewski, R.B. (author), Vladimirescu, A. (author), Babaie, M. (author), Sebastiano, F. (author), Charbon-Iwasaki-Charbon, E. (author)A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum...contribution to periodical 2018
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Chen, Peng (author), Huang, Xiongchuan (author), Chen, Y. (author), Wu, Lianbo (author), Staszewski, R.B. (author)To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order &#x0394;&#x03A3; time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A...journal article 2018
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Kuo, Feng-Wei (author), Babaie, M. (author), Chen, Huan-Neng (Ron) (author), Cho, Lan-Chou (author), Jou, Chewn-Pu (author), Chen, Mark (author), Staszewski, R.B. (author)We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal...journal article 2018
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Bashir, I. (author), Staszewski, R.B. (author), Balsara, Poras T. (author)We present a numerical model of a wideband injection-locked frequency modulator used in a polar transmitter for 3G cellular radio application. At the heart of the system is a self-injection-locked oscillator with a programmable linear tuning range of up to 200 MHz at 4-GHz oscillation frequency. The oscillator is injection locked to a time...journal article 2017
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Tohidian, M. (author), Madadi, I. (author), Staszewski, R.B. (author)The zero/low intermediate frequency (IF) receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In this paper, we propose a new architecture of...journal article 2017