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Kuo, Feng Wei (author), Zong, Z. (author), Chen, Huan Neng Ron (author), Cho, Lan Chou (author), Jou, Chewn Pu (author), Chen, Mark (author), Staszewski, R.B. (author)
This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range,fine-resolution DCO with only switchable metal capacitors. A third-harmonic boosting DCO simultaneously generates 22.5-28 GHz and sufficiently strong 68-84 GHz...
conference paper 2019
document
Kuo, Feng-Wei (author), Babaie, M. (author), Chen, Huan-Neng (Ron) (author), Cho, Lan-Chou (author), Jou, Chewn-Pu (author), Chen, Mark (author), Staszewski, R.B. (author)
We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal...
journal article 2018
document
Kuo, Feng-Wei (author), Binsfeld Ferreira, S. (author), Chen, Huan-Neng Ron (author), Cho, Lan-Chou (author), Jou, Chewn-Pu (author), Hsueh, Fu-Lung (author), Madadi, I. (author), Tohidian, M. (author), Shahmohammadi, M. (author), Babaie, M. (author), Staszewski, R.B. (author)
We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F<sub>2</sub>...
journal article 2017
document
Babaie, M. (author), Kuo, F (author), Chen, H (author), Cho, L (author), Jou, C. P. (author), Hsueh, F. L. (author), Shahmohammadi, M. (author), Staszewski, R.B. (author)
We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup...
journal article 2016
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