Searched for: author%3A%22Bolatkale%2C+M.%22
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Javvaji, L.S. (author), Bolatkale, M. (author), Bajoria, Shagun (author), Rutten, Robert (author), Essink, Bert Oude (author), Beijens, Koen (author), Makinwa, K.A.A. (author), Breems, L.J. (author)
Advances in CMOS technologies and circuit techniques have led to the development of continuous-time delta-sigma modulators (CTΔ Σ Ms) that sample at gigahertz (GHz) frequencies and achieve high linearity [-100 dBc and >120 dBFS spurious-free dynamic ranges (SFDRs)] in wide bandwidths (>100 MHz). However, at low frequencies (≤ 10 MHz),...
journal article 2024
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Javvaji, L.S. (author), Bolatkale, M. (author), Bajoria, Shagun (author), Rutten, Robert (author), Essink, Bert Oude (author), Beijens, Koen (author), Makinwa, K.A.A. (author), Breems, L.J. (author)
Advances in CMOS technologies have led to the development of continuous-time ΔΣ modulators (CTDSMs) with GHz sampling rates that achieve better than-100dBc linearity and bandwidths above 100MHz. However, at low frequencies (below 10MHz), their SNDR is limited by 1/f noise, which limits their use in radio receivers intended to cover both the...
conference paper 2023
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Liu, Qilong (author), Breems, Lucien (author), Zhang, Chenming (author), Bajoria, Shagun (author), Bolatkale, M. (author), Rutten, Robert (author), Radulov, Georgi (author)
In the pursuit of ever larger bandwidths, in recent years GHz-rate continuous-time (CT) oversampled ADCs have been reported in literature that achieve bandwidths of hundreds of MHz and have even exceeded the GHz barrier [1]-[3]. As impressive as these bandwidths are for CT ADCs, the required ADC architectures are complex, are sensitive to...
conference paper 2022
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Mehrotra, Shubham (author), Eland, Efraim (author), Karmakar, S. (author), Liu, Angqi (author), Gonen, B. (author), Bolatkale, M. (author), Van Veldhoven, Robert (author), Makinwa, K.A.A. (author)
This paper presents a continuous-Time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip...
conference paper 2022
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Cenci, P. (author), Bolatkale, M. (author), Rutten, R. (author), Ganzerli, M. (author), Lassche, G. (author), Makinwa, K.A.A. (author), Breems, Lucien (author)
This paper presents a SAR-assisted Continuous-time Delta-Sigma (CT Δ Σ ) ADC, which combines the energy efficiency of SAR ADCs with the relaxed driving requirements of CT Δ Σ ADCs, as well as similar anti-alias filtering. When clocked at 2.4GHz, the ADC achieves 77.5dB SNDR in 40MHz BW. It consumes 3.2mW, resulting in a state-of-the-art...
conference paper 2019
document
Bolatkale, M. (author)
This thesis describes the theory, design and implementation of a high-speed, high-performance continuous-time delta-sigma (CT??) ADC for applications such as medical imaging, high-definition video processing, and wireline and wireless communications. In order to achieve a GHz clocking speed, this thesis investigates excess loop delay...
doctoral thesis 2013
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Bolatkale, M. (author), Breems, LJ (author), Rutten, Robert (author), Makinwa, K.A.A. (author)
A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while...
journal article 2011
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