Searched for: author%3A%22Hamdioui%2C+S.%22
(1 - 8 of 8)
document
Aziza, Hassen (author), Zambelli, Cristian (author), Hamdioui, S. (author), Diware, S.S. (author), Bishnoi, R.K. (author), Gebregiorgis, A.B. (author)
Emerging device technologies such as Resistive RAMs (RRAMs) are under investigation by many researchers and semiconductor companies; not only to realize e.g., embedded non-volatile memories, but also to enable energy-efficient computing making use of new data processing paradigms such as computation-in-memory. However, such devices suffer from...
conference paper 2023
document
Xun, H. (author), Fieback, M. (author), Yuan, S. (author), Aziza, Hassen (author), Heidekamp, Mathijs (author), Copetti, Thiago (author), Poehls, Leticia Bolzani (author), Taouil, M. (author), Hamdioui, S. (author)
Resistive Random Access Memories (RRAMs) are being commercialized with significant investment from several semiconductor companies. In order to provide efficient and high-quality test solutions to push high-volume production, a comprehensive understanding of manufacturing defects is significantly required. This paper identifies and characterizes...
conference paper 2023
document
Xun, H. (author), Yuan, S. (author), Fieback, M. (author), Taouil, M. (author), Hamdioui, S. (author), Aziza, Hassen (author)
Many companies are heavily investing in the commercialization of Resistive Random Access Memories (RRAMs). This calls for a comprehensive understanding of manufacturing defects to develop efficient and high-quality test and diagnosis solutions to push high-volume production. This paper identifies and characterizes a new defect based on silicon...
conference paper 2023
document
Fieback, M. (author), Cardoso Medeiros, G. (author), Wu, L. (author), Aziza, Hassen (author), Bishnoi, R.K. (author), Taouil, M. (author), Hamdioui, S. (author)
Resistive RAM (RRAM) is a promising technology to replace traditional technologies such as Flash, because of its low energy consumption, CMOS compatibility, and high density. Many companies are prototyping this technology to validate its potential. Bringing this technology to the market requires high-quality tests to ensure customer...
journal article 2022
document
Aziza, Hassan (author), Hamdioui, S. (author), Fieback, M. (author), Taouil, M. (author), Moreau, Mathieu (author), Girard, Patrick (author), Virazel, Arnaud (author), Coulié, Karine (author)
RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell ...
journal article 2021
document
Fieback, M. (author), Cardoso Medeiros, G. (author), Gebregiorgis, A.B. (author), Aziza, Hassen (author), Taouil, M. (author), Hamdioui, S. (author)
Industry is prototyping and commercializing Resistive Random Access Memories (RRAMs). Unfortunately, RRAM devices introduce new defects and faults. Hence, high-quality test solutions are urgently needed. Based on silicon measurements, this paper identifies a new RRAM unique fault, the Intermittent Undefined State Fault (IUSF); this fault causes...
conference paper 2021
document
Aziza, H. (author), Moreau, M. (author), Fieback, M. (author), Taouil, M. (author), Hamdioui, S. (author)
Energy efficiency remains one of the main factors for improving the key performance markers of RRAMs to support IoT edge devices. This paper proposes a simple and feasible low power design scheme which can be used as a powerful tool for energy reduction in RRAM circuits. The design scheme is exclusively based on current control during write...
journal article 2020
document
Fieback, M. (author), Wu, L. (author), Cardoso Medeiros, G. (author), Aziza, Hassen (author), Rao, S (author), Marinissen, Erik Jan (author), Taouil, M. (author), Hamdioui, S. (author)
This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach...
conference paper 2019
Searched for: author%3A%22Hamdioui%2C+S.%22
(1 - 8 of 8)