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A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Copetti, T. S. (author), Fieback, M. (author), Gemmeke, T. (author), Hamdioui, S. (author), Poehls, L. M.Bolzani (author)

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible...

journal article 2024

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Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs

Yuan, S. (author), Zhang, Z. (author), Fieback, M. (author), Xun, H. (author), Marinissen, E. J. (author), Kar, G. S. (author), Rao, S. (author), Couet, S. (author), Taouil, M. (author), Hamdioui, S. (author)

The development of Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) mass production requires high-quality test solutions. Accurate and appropriate fault modeling is crucial for the realization of such solutions. This paper targets fault modeling and test generation for all interconnect and contact defects in STT-MRAMs and shows that using the...

conference paper 2023

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Device-Aware Test for Back-Hopping Defects in STT-MRAMs

Yuan, S. (author), Taouil, M. (author), Fieback, M. (author), Xun, H. (author), Marinissen, Erik Jan (author), Kar, Gouri Sankar (author), Rao, Sidharth (author), Couet, Sebastien (author), Hamdioui, S. (author)

The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its...

conference paper 2023

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Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs

Xun, H. (author), Fieback, M. (author), Yuan, S. (author), Zhang, Ziwei (author), Taouil, M. (author), Hamdioui, S. (author)

Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This...

conference paper 2023

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Online Fault Detection and Diagnosis in RRAM

Fieback, M. (author), Bradarić, Filip (author), Taouil, M. (author), Hamdioui, S. (author)

Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and...

conference paper 2023

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Characterization and Test of Intermittent Over RESET in RRAMs

Xun, H. (author), Fieback, M. (author), Yuan, S. (author), Aziza, Hassen (author), Heidekamp, Mathijs (author), Copetti, Thiago (author), Poehls, Leticia Bolzani (author), Taouil, M. (author), Hamdioui, S. (author)

Resistive Random Access Memories (RRAMs) are being commercialized with significant investment from several semiconductor companies. In order to provide efficient and high-quality test solutions to push high-volume production, a comprehensive understanding of manufacturing defects is significantly required. This paper identifies and characterizes...

conference paper 2023

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Device Aware Diagnosis for Unique Defects in STT-MRAMs

Aouichi, A. (author), Yuan, S. (author), Fieback, M. (author), Rao, Siddharth (author), Kim, Woojin (author), Marinissen, Erik Jan (author), Couet, Sebastien (author), Taouil, M. (author), Hamdioui, S. (author)

Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) are on their way to commercialization. However, obtaining high-quality test and diagnosis solutions for STT-MRAMs is challenging due to the existence of unique defects in Magnetic Tunneling Junctions (MTJs). Recently, the Device-Aware Test (DA-Test) method has been put forward as an effective...

conference paper 2023

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Dependability of Future Edge-AI Processors: Pandora’s Box

Gomony, Manil Dev (author), Gebregiorgis, A.B. (author), Fieback, M. (author), Geilen, Marc (author), Stuijk, Sander (author), Richter-Brockmann, Jan (author), Bishnoi, R.K. (author), Taouil, M. (author), Hamdioui, S. (author)

This paper addresses one of the directions of the HORIZON EU CONVOLVE project being dependability of smart edge processors based on computation-in-memory and emerging memristor devices such as RRAM. It discusses how how this alternative computing paradigm will change the way we used to do manufacturing test. In addition, it describes how these...

conference paper 2023

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Device-Aware Test for Ion Depletion Defects in RRAMs

Xun, H. (author), Yuan, S. (author), Fieback, M. (author), Taouil, M. (author), Hamdioui, S. (author), Aziza, Hassen (author)

Many companies are heavily investing in the commercialization of Resistive Random Access Memories (RRAMs). This calls for a comprehensive understanding of manufacturing defects to develop efficient and high-quality test and diagnosis solutions to push high-volume production. This paper identifies and characterizes a new defect based on silicon...

conference paper 2023

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Defects, Fault Modeling, and Test Development Framework for RRAMs

Fieback, M. (author), Cardoso Medeiros, G. (author), Wu, L. (author), Aziza, Hassen (author), Bishnoi, R.K. (author), Taouil, M. (author), Hamdioui, S. (author)

Resistive RAM (RRAM) is a promising technology to replace traditional technologies such as Flash, because of its low energy consumption, CMOS compatibility, and high density. Many companies are prototyping this technology to validate its potential. Bringing this technology to the market requires high-quality tests to ensure customer...

journal article 2022

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Structured Test Development Approach for Computation-in-Memory Architectures

Fieback, M. (author), Taouil, M. (author), Hamdioui, S. (author)

Testing of Computation-in-Memory (CIM) designs based on emerging non-volatile memory technologies, such as resistive RAM (RRAM), is fundamentally different from testing traditional memories. Such designs allow not only for data storage (i.e., memory configuration) but also for the execution of logical and arithmetic operations (i.e., computing...

conference paper 2022

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Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

Copetti, T.S. (author), Nilovic, M. (author), Fieback, M. (author), Gemmeke, T. (author), Hamdioui, S. (author), Bolzani Poehls, L.M. (author)

Memristive devices have become promising candidates to complement and/or replace the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are...

conference paper 2022

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Hierarchical Memory Diagnosis

Cardoso Medeiros, G. (author), Fieback, M. (author), Gebregiorgis, A.B. (author), Taouil, M. (author), Poehls, L. B. (author), Hamdioui, S. (author)

High-quality memory diagnosis methodologies are critical enablers for scaled memory devices as they reduce time to market and provide valuable information regarding test escapes and customer returns. This paper presents an efficient Hierarchical Memory Diagnosis (HMD) approach that accurately diagnoses faults in the entire memory. Faults are...

conference paper 2022

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Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT

Singh, A. (author), Fieback, M. (author), Bishnoi, R.K. (author), Bradarić, Filip (author), Gebregiorgis, A.B. (author), Joshi, R.V. (author), Hamdioui, S. (author)

Emerging non-volatile resistive RAM (RRAM) device technology has shown great potential to cultivate not only high-density memory storage, but also energy-efficient computing units. However, the unique challenges related to RRAM fabrication process render the traditional memory testing solutions inefficient and inadequate for high product quality...

conference paper 2022

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PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Fieback, M. (author), Münch, Christopher (author), Gebregiorgis, A.B. (author), Cardoso Medeiros, G. (author), Taouil, M. (author), Hamdioui, S. (author), Tahoori, Mehdi (author)

Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the...

conference paper 2022

document

Using Hopfield Networks to Correct Instruction Faults

Köylü, T.C. (author), Fieback, M. (author), Hamdioui, S. (author), Taouil, M. (author)

Fault injection attacks pose an important threat to security-sensitive applications, such as secure communication and storage. By injecting faults into instructions, an attacker can cause information leakage or denial-of-service. Hence, it is important to secure the sensitive parts not only by detecting faults in the executed instructions but...

conference paper 2022

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Recent Trends and Perspectives on Defect-Oriented Testing

Bernardi, P. (author), Cantoro, R. (author), Coyette, A. (author), Dobbeleare, W. (author), Fieback, M. (author), Floridia, A. (author), Gielenk, G. (author), Guerriero, A. M. (author), Hamdioui, S. (author)

Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips...

conference paper 2022

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Multi-level control of resistive ram (Rram) using a write termination to achieve 4 bits/cell in high resistance state

Aziza, Hassan (author), Hamdioui, S. (author), Fieback, M. (author), Taouil, M. (author), Moreau, Mathieu (author), Girard, Patrick (author), Virazel, Arnaud (author), Coulié, Karine (author)

RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell ...

journal article 2021

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Review of Manufacturing Process Defects and Their Effects on Memristive Devices

Poehls, L. M.Bolzani (author), Fieback, M. (author), Hoffmann-Eifert, S. (author), Copetti, T. (author), Brum, E. (author), Menzel, S. (author), Hamdioui, S. (author), Gemmeke, T. (author)

Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective...

journal article 2021

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Hard-to-Detect Fault Analysis in FinFET SRAMs

Cardoso Medeiros, G. (author), Fieback, M. (author), Wu, L. (author), Taouil, M. (author), Bolzani Poehls, L. M. (author), Hamdioui, S. (author)

Manufacturing defects can cause hard-to-detect (HTD) faults in fin field-effect transistor (FinFET) static random access memories (SRAMs). Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field...

journal article 2021