A 10-b 330nW Third-Order Predictive SAR ADC Dedicated to Neural Recording Brain Implants

This paper reports on a predictive analog-todigital converter (ADC). The proposed ADC employs a linear predictive filter to prepare a prediction for the current sample based on the values of the previous digital codes. This leads to significant reduction in the mean bit cycle of the converter. It is shown in this work that this idea is...

Speed-Power Improvement in High-Voltage Switches Employed in Multi-Electrode Arrays

In multi-electrode arrays (MEAs), for electrical recording and electrical stimulation, high voltage (HV) switches are employed to build an analog multiplexer to conduct either a HV stimulation signal from the pulse generator circuit to an electrode or a low-voltage noise-sensitive signal from the electrode to a recording stage. In this brief,...

Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition

Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to...

A Charge-Redistribution Phase-Domain ADC Using an IQ-Assisted Binary-Search Algorithm

Phase-domain Analog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementation of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer...