Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space...

Is RISC-V ready for Space? A Security Perspective

Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and...

Simplified Procedures for COTS TID Testing: A Comparison between ⁹⁰Sr and ⁶⁰Co

The tolerance to the cumulative effects of ionizing radiation is one of the most important parameters to keep into account when selecting an EEE component for space applications. TID sensitivity is normally investigated measuring changes induced by gamma rays from 60Co sources to nominal parameters of a component or to its expected functional...

Towards defining a simplified procedure for COTS system-on-chip TID testing

The use of System-on-Chip (SoC) solutions in the design of on-board data handling systems is an important step towards further miniaturization in space. However, the Total Ionizing Dose (TID) and Single Event Effects (SEE) characterization of these complex devices present new challenges that are either not fully addressed by current testing...