Microfabricated albedo insensitive sun position sensor system in silicon carbide with integrated 3D optics and CMOS electronics

The next generation of satellites will need to tackle tomorrow's challenges for communication, navigation and observation. In order to do so, it is expected that the amount of satellites in orbit will keep increasing, form smart constellations and miniaturize individual satellites to make access to space cost effective. To enable this next...

Integrated Digital and Analog Circuit Blocks in a Scalable Silicon Carbide CMOS Technology

The wide bandgap of silicon carbide (SiC) has attracted a large interest over the past years in many research fields, such as power electronics, high operation temperature circuits, harsh environmental sensing, and more. To facilitate research on complex integrated SiC circuits, ensure reproducibility, and cut down cost, the availability of a...

Integrated 64 pixel UV image sensor and readout in a silicon carbide CMOS technology

This work demonstrates the first on-chip UV optoelectronic integration in 4H-SiC CMOS, which includes an image sensor with 64 active pixels and a total of 1263 transistors on a 100 mm2 chip. The reported image sensor offers serial digital, analog, and 2-bit ADC outputs and operates at 0.39 Hz with a maximum power consumption of 60 μW, which are...

Visible Blind Quadrant Sun Position Sensor in a Silicon Carbide Technology

In this paper, we present a quadrant sun position sensor microsystem device in a silicon carbide technology that operates in a field-of-view of ±33° and reaches a mean error of 1.9° in this range. This will allow, for the first time, an inherently visible blind sun position sensor in a CMOS compatible technology. Opto-electronic integration of...

Resistive and CTAT Temperature Sensors in a Silicon Carbide CMOS Technology

Accurately sensing the temperature in silicon carbide (power) devices is of great importance to their reliable operation. Here, temperature sensors by resistive and CMOS structures are fabricated and characterized in an open silicon carbide CMOS technology. Over a range of 25-200°C, doped design layers have negative temperature coefficients of...